Enhanced storage states in an memory

Details Enhanced storage states in an memory Enhanced storage states in an memory

2002-05-17

2004-10-19

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S227000

Reexamination Certificate

active

06807080

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of random access memories. More particularly, this invention relates to storage states in a memory cell.
2. Art Background
A typical random access memory includes an array of storage cells. Each storage cell typically includes a storage structure which is capable of changing storage states. For example, a storage cell in a ferroelectric random access memory (FeRAM) typically includes a ferroelectric capacitor capable of changing stored charge polarities.
The storage state of a storage cell typically indicates its logic state. A storage cell is usually written by applying programming voltages which alter its storage state. For example, an FeRAM storage cell is usually written applying programming voltages that alter the charge polarities of its ferroelectric capacitor.
It is usually desirable to provide a storage cell that enhances the likelihood that its storage state will be discernable during a read operation. Unfortunately, structures in a storage cell that are used for storage cell access may reduce the discernability of its storage states. In an FeRAM storage cell, for example, a programming voltage is usually applied to the ferroelectric capacitor through an access transistor. Unfortunately, the access transistor usually degrades the amount of programming voltage that reaches the ferroelectric capacitor, thereby limiting the amount of electrical charge that it accumulates.
One prior method for avoiding such voltage degradation during programming is to apply boosted voltage levels during programming. In programming a typical prior FeRAM cell, for example, a supply-level voltage (V
DD
) is usually applied the access transistor of the storage cell and a boosted supply-level voltage (V
PP
) is usually applied to a control gate of the access transistor. Typically, V
PP
is greater than V
DD
by a threshold voltage (V
TH,be
) to enable a maximum amount of charge to pass through the access transistor and to the ferroelectric capacitor. Unfortunately, high levels of V
PP
may damage the gate structure of the access transistor, thereby reducing the reliability and service life of the memory. Similar problems may be encountered in other types of memories.
SUMMARY OF THE INVENTION
A memory is disclosed with mechanisms for enhancing storage states without boosting voltages to levels that damage storage cell structures. A storage cell according to the present teachings includes a storage structure capable of switching storage states. A memory according to the present teachings includes means for writing the storage cell by applying a first voltage to a first node of the storage structure and for applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities. The magnitude of the second voltage is selected to enhance the overall voltage applied to the storage structure during programming.
Other features and advantages of the present invention will be apparent from the detailed description that follows.


REFERENCES:
patent: 5455786 (1995-10-01), Takeuchi et al.
patent: 5798964 (1998-08-01), Shimizu et al.
patent: 6201731 (2001-03-01), Kamp et al.
patent: 6236607 (2001-05-01), Schlager et al.
patent: 6541375 (2003-04-01), Hayashi et al.

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