Enhanced STCX design to improve subsequent load efficiency

Details Enhanced STCX design to improve subsequent load efficiency Enhanced STCX design to improve subsequent load efficiency

2007-08-07

2007-08-07

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S135000

Reexamination Certificate

active

11082761

ABSTRACT:
A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, invalidating data for the address in a store-through upper level cache, and placing data returned from the lower level cache into the store-through upper level cache.

REFERENCES:
patent: 5706464 (1998-01-01), Moore et al.
patent: 6021261 (2000-02-01), Barrett et al.
patent: 7089373 (2006-08-01), Day et al.
patent: 7197604 (2007-03-01), Guthrie et al.
patent: 2006/0085603 (2006-04-01), Guthrie et al.
patent: 2006/0085604 (2006-04-01), Guthrie et al.
patent: 2006/0271744 (2006-11-01), Goodman et al.
patent: 2007/0033345 (2007-02-01), Guthrie et al.

Affiliated with

Also associated with

Rating

Enhanced STCX design to improve subsequent load efficiency does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhanced STCX design to improve subsequent load efficiency, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced STCX design to improve subsequent load efficiency will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3885852