Enhanced speed sorting of microprocessors at wafer test

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S762050

Reexamination Certificate

active

08049526

ABSTRACT:
A method and apparatus are provided for implementing optimized speed sorting of microprocessors at wafer test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into appropriate speed bins. The method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods.

REFERENCES:
patent: 6459293 (2002-10-01), Keshavarzi et al.
patent: 6625758 (2003-09-01), Singh

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