Enhanced shallow junction design by polysilicon line width reduc

Details Enhanced shallow junction design by polysilicon line width reduc Enhanced shallow junction design by polysilicon line width reduc

1998-11-05

1999-11-09

Wilczewski, Mary

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438303, 438290, H01L 21336, H01L 2128

Patent

active

059813687

ABSTRACT:
A method of forming a transistor includes forming a gate dielectric layer upon a substrate, forming a polysilicon layer upon the gate dielectric layer and then forming a thin nitride layer upon the gate polysilicon layer. The thin nitride layer is then pattern etched to define a nitride cap above a future channel. The gate polysilicon layer and a portion of the silicon substrate below the gate dielectric layer is then doped with arsenic. An optional annealing step then causes some of the arsenic to migrate below the nitride cap. A subsequent oxidation step then causes gate conductor/gate oxide stacks with integrated spacers to be defined below the nitride cap. The oxidation step and optional prior annealing step also cause some arsenic to migrate into the channel to form the LDD regions. The substrate is etched to remove portions of the gate polysilicon layer unprotected by the nitride cap. The remaining gate structures below the nitride cap include spacers and LDD regions are formed about the polysilicon gate conductor with the combined structure having a width of the nitride cap. Accordingly, the channel width has been decreased to a size that is even smaller than the width of the nitride cap.

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patent: 5130264 (1992-07-01), Troxell et al.
patent: 5776821 (1998-07-01), Haskell et al.

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