Enhanced retention time for embedded dynamic random access...

Details Enhanced retention time for embedded dynamic random access... Enhanced retention time for embedded dynamic random access...

2005-01-25

2005-01-25

Tran, Thien F (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S313000, C257S297000

Reexamination Certificate

active

06847076

ABSTRACT:
Increasing the retention time of an embedded dynamic random access memory (DRAM) is disclosed. An embedded DRAM includes a metal oxide semiconductor (MOS) capacitor. The capacitor has a storage node formed between a P+ doped region and a polysilicon plate within an N well. An N− doped region is situated substantially completely under the polysilicon plate and substantially under the P+ doped region. The presence of the N− doped region decreases the threshold voltage of the capacitor and reduces effectively the junction leakage current to the N well, achieving a larger retention time.

REFERENCES:
patent: 5023750 (1991-06-01), Hirayama
patent: 5033022 (1991-07-01), Segawa
patent: 6785157 (2004-08-01), Arimoto et al.

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