Enhanced planarization technique for an integrated circuit

Details Enhanced planarization technique for an integrated circuit Enhanced planarization technique for an integrated circuit

1997-11-24

1998-11-17

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438723, 216 38, H01L 2100

Patent

active

058376135

ABSTRACT:
A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

REFERENCES:
patent: 4253907 (1981-03-01), Parry et al.
patent: 4354896 (1982-10-01), Hunter
patent: 4384938 (1983-05-01), Desilets et al.
patent: 4654112 (1987-03-01), Douglas et al.
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4660278 (1987-04-01), Teng
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4721548 (1988-01-01), Morimoto
patent: 4755476 (1988-07-01), Bohm et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4801560 (1989-01-01), Wood et al.
patent: 4824767 (1989-04-01), Chambers et al.
patent: 4872947 (1989-10-01), Wang et al.
patent: 4894351 (1990-01-01), Batty
patent: 4912061 (1990-03-01), Nasr et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5003062 (1991-03-01), Yen
patent: 5063176 (1991-11-01), Lee et al.
patent: 5110763 (1992-05-01), Matsumoto
patent: 5117273 (1992-05-01), Stark et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5166088 (1992-11-01), Ueda et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250472 (1993-10-01), Chen et al.
patent: 5266525 (1993-11-01), Morozumi
patent: 5310720 (1994-05-01), Shin et al.
patent: 5320983 (1994-06-01), Ouellet
patent: 5399389 (1995-03-01), Hieber et al.
patent: 5435888 (1995-07-01), Kalnitsky et al.
"Advantages of using spin on glass layer in interconnection dielectric planarization," Microelectronic Engineering, vol. 5 (1986).
"Doped silicon oxide deposition by atmospheric pressure and low temperature chemical vapor deposition using tetraethoxysilane and ozone," Fujino et al., J. Electrochem. Society, vol. 138, No. 10, p. 3019.
"Polysilicon planarization using spin-on glass," S. Ramaswami and A. Nagy, J. Electrochem. Soc., vol. 139, No. 2, p. 591 (1992).
"Three `Low Dt` options for planarizing the premetal dielectric on an advanced double poly BiCMOS process," by W. Dauksher, M. Miller, and C. Tracey, J. Electrochem. Soc., vol. 139, No. 2, p. 532 (1992).
"The effect of plasma cure temperature on spin-on glass," by H. Namatsu and K. Minegishi, J. Electrochem. Soc., vol. 140, No. 4, p. 140 (1991).
"Hot-carrier aging of the MOS transistor in the presence of spin-on glass as the interlevel dielectric," by N. Lifshitz and G. Smolinsky, IEEE Electron Device Letters, vol. 12, No. 3, p. 140 (1991).
"Etching--Applications and trends of dry etching," by L.M. Ephrath and G.S. Mathad, Handbook of Advanced Technology and Computer Systems at 27 ff (1988).
"Reactive ion etching," by B. Gorowitz and R. Saia, 8 VLSI Electronics, 297ff (1984).
Patent Abstracts of Japan, vol. 15, No. 348 (E-1107) 4 Sep. 1991 & JP-A-31 33 131 (Mitsubishi Electric Corp.) 6 Jun. 1991.
IBM Technical Dislosure Bulletin, vol. 30, No. 8, p. 252, Jan. 1988.
IBM Technical Dislosure Bulletin, vol. 29, No. 3, p. 1328, Aug. 1986.
"A new technology for oxide contact and via etch," by Pete Singer, Semiconductor International, p. 36 (1993).
Handbook on Semiconductors, (ed. C. Holson), vol. 4, p. 208 (1981).
"Etching applications and trends of dry etching," Ephrath et al., Semiconductor Technology and Computer Systems, Ch. 2, p. 26.
VLSI Electronics Microstructure Science, vol. 8, ed. Norman Einspruch, p. 298 (1984).
"Plasma etch anisotrophy," C.B. Zarowin, J. Electrochem. Soc., Solid-State Science and Technology, p. 1144 (1983).
"A super self-aligned source/drain MOSFET," Lau et al., IEDM, p. 358 (1987).
"A margin-free contact process using an AL.sub.3 O.sub.3 etch-stop layer for high density devices," Fukase et al., IEDM, p. 837 (1992).
VLSI Fabrication Principles, Silicon and Callium Arsenide, by Sorab K. Ghandi.
Research Disclosure, No. 282, Oct. 1987, Havant GB p. 608, "Spin on glass insulator enhancement".

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