Enhanced planarization technique for an integrated circuit

Details Enhanced planarization technique for an integrated circuit Enhanced planarization technique for an integrated circuit

1993-12-06

1995-07-25

Dang, Thi

Etching a substrate: processes

Forming or treating electrical conductor article

Forming or treating of groove or through hole

437228, 437231, 437235, 437238, 216 80, 216 97, H01L 2100

Patent

active

054358884

ABSTRACT:
A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

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