Enhanced peripheral component interconnect bus protocol

Details Enhanced peripheral component interconnect bus protocol Enhanced peripheral component interconnect bus protocol

1996-09-11

1997-11-18

Harvey, Jack B.

395880, G06F 1300

Patent

active

056896603

ABSTRACT:
A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data at higher data rates that the bus clock speed. By transferring data more than once per clock cycle, the data transfer rate is multiplied. Another feature of the present invention is a protocol allowing a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.

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PCI Local Bus Specification, Revision 2.0; PCI Special Interest Group Jun. 22, 1992.

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