Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-06-14
2005-06-14
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S008000, C710S060000, C710S315000, C710S061000, C713S501000
Reexamination Certificate
active
06907487
ABSTRACT:
A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.
REFERENCES:
patent: 5548733 (1996-08-01), Sarangdhar et al.
patent: 5568620 (1996-10-01), Sarangdhar et al.
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5615343 (1997-03-01), Sarangdhar et al.
patent: 5796977 (1998-08-01), Sarangdhar et al.
patent: 5812803 (1998-09-01), Pawlowski et al.
patent: 5838995 (1998-11-01), Chen et al.
patent: 5844858 (1998-12-01), Kyung
patent: 5903738 (1999-05-01), Sarangdhar et al.
patent: 5919254 (1999-07-01), Pawlowski et al.
patent: 5937171 (1999-08-01), Sarangdhar et al.
patent: 5964856 (1999-10-01), Wu et al.
patent: 5978869 (1999-11-01), Gutherie et al.
patent: 5999023 (1999-12-01), Kim
patent: 6081877 (2000-06-01), Taki
patent: 6092156 (2000-07-01), Schibinger et al.
patent: 6102118 (2000-08-01), Moore
patent: 6108736 (2000-08-01), Bell
patent: 6405271 (2002-06-01), MacWilliams et al.
patent: 6449677 (2002-09-01), Olarig et al.
patent: 6487621 (2002-11-01), MacLaren
patent: 6601121 (2003-07-01), Singh et al.
patent: 6609171 (2003-08-01), Singh et al.
patent: 2001/0007999 (2001-07-01), Rasmussen et al.
patent: 2001/0037424 (2001-11-01), Singh et al.
patent: 2002/0147875 (2002-10-01), Singh et al.
patent: 706137 (1996-04-01), None
patent: WO 9524678 (1995-09-01), None
patent: WO 99/36858 (1999-07-01), None
“Protocol Extensions to Microprocessor Memory Bus to Support Extended Address Space,” May 1, 1994, IBM, vol. 37, Issue 5 p. 389-390.
Picker, D., et al., “Enhancing SCI's Fairness Protocol for Increased Throughput,” Oct. 19-22, 1993, IEEE 1993 International Conference on Network Protocols, p. 292-299.
Mindshare, Inc., Tom Shanley, Pentium® Pro and Pentium® II System Architecture Second Edition, Addison-Wesley, 1998, 180 pages.
Intel Corporation, “Accelerated Graphics Port Interface Specification,” Revision 1.0, Jul. 31, 1996.
Intel®, Pentium® II Processor Developer's Manual, Chapters 1-6, Oct. 1997.
Intel Corporation, “Intel Multibus® Specification”, 1978.
Intel Corporation, “Multibus® II Bus Architecture Specification Handbook,” 1984.
Intel Corporation, “High-Performance Synchronous 32-Bit Bus: Multibus II,”.
Greiner Robert J.
Hill David L.
Parker Donald D.
Pawlowski Stephen S.
Singh Gurbir
Draeger Jeffery S.
Mason Donna K.
Rinehart Mark H.
LandOfFree
Enhanced highly pipelined bus architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced highly pipelined bus architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced highly pipelined bus architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3477021