Enhanced glitch removal circuit

Details Enhanced glitch removal circuit Enhanced glitch removal circuit

1999-10-21

2001-06-19

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Pulse shaping

C326S093000, C326S026000

Reexamination Certificate

active

06249141

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to signal improvement circuits, and in particular, relates to circuits for removal of glitch signals from periodic waveforms such as clock signals.
2. Description of the Prior Art
Electrical circuits, including circuits packaged in integrated circuits (ICs), often have to operate in noisy and hostile environments where spurious pulses (also referred to as glitch signals) may be generated in the process. Glitch signals if untreated may affect the operation of the circuit and hamper the performance of the entire system. Thus, circuits must be designed to anticipate and handle the spurious pulses or glitch signals in order to maintain consistency and reliability of circuit operation.
Signals that are affected by a noisy environment where glitch signals are generated includes clock signals and handshake signals, which drive the various circuitry within a system. Referring to
FIG. 1
, a clock signal is depicted in the form of a repetitive sequence of pulses where high voltage levels followed by low voltage levels. The high voltage levels digitally represent “1”s and the low voltage levels digitally represent “0”s.
The clock signal may become noisy and deviate from its original rectangular shape by the time it reaches its destination terminal.
FIG. 2
illustrates a clock signal having several possible glitch signals therein. A glitch signal following the falling edge
10
of a clock pulse is indicated at
12
, where the signal occurs within a time period “d” from the falling edge
10
. Another glitch signal closer in time preceding the rising edge
14
of a second clock pulse is indicated at
16
. A glitch signal may also occur within a high clock pulse causing a temporarily drop of the pulse from a high voltage level to a low voltage level, such as the glitch signals indicated at
18
and
20
. Note that glitch signals may be of any shape and duration (though typically are transient).
These glitch signals can be easily categorized into two types. The first type occurs while the clock signal is in the low voltage state and is as illustrated by glitch signals at
12
and
16
. The second type occurs while the clock signal is in the high state and is as illustrated by glitch signals at
18
and
20
.
Ideally, circuits encountering these types of glitch signals should eliminate them and restore the signal to its original shape. The disclosure herein focuses on circuits for eliminating glitch signals of the first type.
Prior art circuits for eliminating glitch signals of the first type remove a glitch signal occurring either preceding the rising edge of a pulse or occurring following the falling edge of a clock pulse but not near both edges. Referring to
FIG. 3
a
, a prior art glitch-eater circuit for eliminating glitch signals occurring following the falling edge of a clock pulse is illustrated. The circuit comprises an OR gate
30
and a delay cell
32
. The input signal is routed to one input of the OR gate
30
and to the input of the delay cell
32
; the output of the delay cell
32
is routed to the other input of the OR gate
30
. Referring to
FIG. 3
b
, a clock signal, having a glitch signal following near the falling edge of a clock pulse and a glitch signal preceding the rising edge of another clock pulse as illustrated at
34
and
36
respectively, is processed through the delay cell (
FIG. 3
a
,
32
) and the OR gate (
FIG. 3
a
,
30
). In this circuit, for a time period “d” after any pulse has gone from a high voltage level to a low voltage level, the output of the delay cell remains high and consequently causes the OR gate to produce a high signal for a time duration “d” after any falling edge has occurred. Thus, upon encountering a glitch signal occurring within a period “d” from the falling edge of a clock signal, the circuit will cause the clock signal to remain high for an additional time period “d” as illustrated in
FIG. 3
c
, after the occurrence of the falling edge of the glitch signal (
FIG. 3
b
,
38
) (not the falling edge of the clock signal). Note that the second glitch signal
36
preceding the rising edge of the next clock pulse is not eliminated at all.
In another prior art circuit illustrated in
FIG. 4
a
, a glitch-eater circuit for eliminating a glitch signal preceding the rising edge of a clock pulse is illustrated. Here, the circuit comprises a two-input AND gate
40
and a delay cell
42
. The input signal is passed to one leg of the AND gate
40
and to the input of the delay cell
42
. The output of the delay cell is passed to the second leg of the AND gate
40
. Referring to
FIG. 4
b
, an input signal contains a first glitch signal
44
following the falling edge of a first clock pulse and a glitch signal
46
preceding the rising edge of a second clock pulse. This circuit will not handle glitch signals occurring within a time period “d” from the falling edge of the clock pulse. However, upon the occurrence of the rising edge
45
of a pulse
46
, the delay cell (
FIG. 4
a
,
42
) is still producing a low signal to the AND gate thereby causing the AND gate output signal to be low. In effect, this circuit delays a rising edge (and therefore a pulse) by a time period “d” and eliminates a glitch signal in the process.
FIG. 4
c
illustrates the output of this circuit.
The two above prior art circuits were designed to handle glitch signals occurring near either the rising edges or the falling edges of signal pulses, but not both. It would be desirable to have a single circuit that can handle glitch signals occurring near both edges. Although, conceivably, the two circuits may be combined in some manner to achieve the same effect, the disadvantage with such approach is that there would be redundant and unnecessary circuitry.
SUMMARY OF THE INVENTION
Therefore, an objective of the present invention is to provide a circuit for eliminating glitch signals occurring near both the falling edge and rising edge of a signal pulse.
It is another object of the present invention to provide a simple yet reliable circuit for the removal of glitch signals in a periodic pulse.
Briefly, an enhanced glitch-eater circuit in accordance with a presently preferred embodiment of the present invention comprises an inverter connected between a circuit input terminal and a transmission gate which is controlled by a two-input XNOR (exclusive-NOR) gate and outputs to a latch coupled to a circuit output terminal. The XNOR gate receives the latched output signal at one of its inputs and a delayed latched signal at its other input, the delayed latched signal being generated by a delay cell receiving its input from the latch. The signal stored in the latch may be reset by the use of a simple transistor connected to a voltage source.
An advantage of the present invention is that it provides a circuit for eliminating glitch signals occurring near both the falling edges and rising edges of clock pulses.
Another advantage of the present invention is that it provides a simple yet reliable circuit for the removal of glitch signals in a periodic pulse train.
These and other features and advantages of the present invention will be understood upon examining the figures and reading the following detailed description of preferred embodiment of the invention.


REFERENCES:
patent: 5168181 (1992-12-01), Baiocchi et al.
patent: 5723993 (1998-03-01), Cha
patent: 5959465 (1999-09-01), Beat

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