Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-05-04
2001-04-24
Sheikh, Ayaz (Department: 2155)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C714S006130, C714S006130, C714S053000, C714S054000, C714S723000, C714S042000, C714S043000, C714S044000, C714S056000
Reexamination Certificate
active
06223299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to bus error handling and in particular to handling bus errors during load and store operations. Still more particularly, the present invention relates to preventing damage from bus errors during load and store operations through forced bad data parity or zero byte enables thereby enhancing the capability of recovering from such errors.
2. Description of the Related Art
Many data processing systems support a standard input/output (I/O) systems conforming to the peripheral component interconnect (PCI) Local Bus architecture, an architecture supporting many complex features including I/O expansion through PCI-to-PCI bridges, peer-to-peer (device-to-device) data transfers, multi-function devices, and both integrated and plug-in devices. In setting up I/O operations to I/O devices on a PCI bus, the device driver must perform a series of load and/or store operations to the I/O device. If any of these operations gets a parity error on the I/O bus, it is necessary to get this information back to the device driver so that the device driver can stop before the operation is initiated.
As an example, a first store operation may be employed to set up an address in the I/O device, followed by a second store operation signalling the I/O device to begin the data transfer. If the first store operation gets an error and the second store operation is then received, the I/O device might start the operation to the incorrect location. The PCI architecture includes no provision for designing adapters to prevent load and/or store operations from continuing after an error. Most contemporary systems allow device driver execution to continue after a store operation rather than wait for a “successful” response to the store operation to determine if it completely correctly. This is preferable since the processor stall required to wait for a response to store operations would vastly degrade system performance.
One technique allowing the device driver to prevent subsequent load and/or store operations from completing after an error without waiting for the response to every load or store operation is for the device driver to read back all of the setup information before issuing the “go” store operation (the store operation signalling the device driver to begin) and then compare the read back data with the stored data to determine if the two are the same prior to issuing the “go” store operation. However, this requires a lot of processor time for the load operations out to the device, a long path, in many cases, relative to processor instruction times. Another possible solution is to examine bits within the interface or status registers within the I/O device to determine whether an error has occurred after a store operation. This, however, is unsupported by current architectures and also requires a lot of processor time.
Yet another solution is for an I/O device to generate an external interrupt when there is an error after a store operation, but waiting for an interrupt before continuing takes a lot of time. Other conceivable possibilities will generally be adapter dependent, and thus incapable of working with any I/O device not designed for that solution, or will require a lot of processor time.
It would be desirable, therefore, to provide a method and apparatus for preventing load and/or store operations from completing after an error without waiting for a response to every load or store operation. It would also be advantageous for the mechanism to avoid requiring changes to PCI adapter or I/O device hardware, so that the mechanism may be employed with any I/O device, even if not designed specifically for that mechanism.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a method and apparatus for bus error handling.
It is another object of the present invention to provide a method and apparatus for handling bus errors during load and store operations.
It is yet another object of the present invention to provide a method and apparatus for preventing damage from bus errors during load and store operations through identification of a device which previously encountered an error by use of forced bad data parity or zero byte enables.
The foregoing objects are achieved as is now described. Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5313627 (1994-05-01), Amini et al.
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5499346 (1996-03-01), Amini et al.
patent: 5581714 (1996-12-01), Amini et al.
patent: 5790831 (1998-08-01), Lin et al.
patent: 5815647 (1998-09-01), Buckland et al.
patent: 5857080 (1999-01-01), Jander et al.
patent: 5857085 (1999-01-01), Zhang et al.
patent: 5859988 (1999-01-01), Ajanovic et al.
patent: 5872910 (1999-02-01), Kuslak et al.
Bossen Douglas Craig
McLaughlin Charles Andrew
Neal Danny Marvin
Nicholson James Otto
Thurber Steven Mark
Emile Volel
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Jean Frantz B.
Sheikh Ayaz
LandOfFree
Enhanced error handling for I/O load/store operations to a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced error handling for I/O load/store operations to a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced error handling for I/O load/store operations to a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523862