Enhanced dual port I/O bus bridge

Details Enhanced dual port I/O bus bridge Enhanced dual port I/O bus bridge

1997-03-21

2000-03-28

Auve, Glenn A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395308, 711149, G06F 1340

Patent

active

060442077

ABSTRACT:
An enhanced performance dual port I/O bus bridge to connect a first I/O bus of bandwidth B and a second like-type I/O bus of bandwidth B with a simultaneously bi-directional data path operating at a bandwidth of at least B and typically at a bandwidth of from 2B to 4B. The enhanced dual port I/O bus bridge includes a first bridge interface and a second bridge interface to a first I/O bus and a second I/O bus respectively. The bridge also includes a first data access path buffering data and having a bandwidth of at least B between the first bridge interface and a data cache, and a second data access path buffering data and having a bandwidth of at least B between the second bridge interface and the same data cache. The data cache can be a RAID type cache. The enhanced I/O bus bridge is operated asynchronously by a means for controlling simultaneous bi-directional data flow between the first bridge interface and the second bridge interface by way of concurrent dual port access to the shared data cache.

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PCI Special Interest Group: PCI to PCI Bridge Architecture Specification, Revision 1.0, Apr. 5, 1994, pp. 1-7.

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