Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-07-03
1999-03-23
Swann, Tod
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
36518905, 365203, 36523008, G06F 1200
Patent
active
058872728
ABSTRACT:
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
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Carrigan Donald G.
Jones Oscar Frederick
Mobley Kenneth J.
Sartore Ronald H.
Casey Michael R.
Chow Christopher
Enhanced Memory Systems Inc.
Kubida William J.
Meza Peter J.
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