Enhanced capacitor shape

Details Enhanced capacitor shape Enhanced capacitor shape

1998-02-23

2002-04-09

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S309000

Reexamination Certificate

active

06369432

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to integrated circuits and more particularly to the shape of a container capacitor for use in an integrated circuit.
BACKGROUND OF THE INVENTION
Capacitors are used in a wide variety of semiconductor circuits. Capacitors are of special concern in DRAM (dynamic random access memory) memory circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in any other type of memory circuit, such as an SRAM (static random access memory), as well as in any other circuit in which capacitors are used.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
10
. For each cell, one side of the storage capacitor
14
is connected to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1” signal) of the circuit. The other side of the storage capacitor
14
is connected to the drain of the access field effect transistor
12
. The gate of the access field effect transistor
12
is connected to a signal referred to as the word line
18
. The source of the field effect transistor
12
is connected to a signal referred to as the bit line
16
. With the circuit connected in this manner, it is apparent that the word line controls access to the storage capacitor
14
by allowing or preventing the signal (a logic “0” or a logic “1”) on the bit line
16
to be written to or read from the storage capacitor
14
.
The manufacturing of a DRAM cell therefore includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage.
DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. For example, use of the invention in trench or planar capacitors is also possible.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) having an oval or circular cross section. The wall of the tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric. The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name “container capacitor.” Although the invention will be further discussed in connection with stacked container capacitors, the invention should not be understood to be limited thereto.
FIG. 2
illustrates a top view of a portion of a known DRAM memory circuit from which the upper layers have been removed to reveal container capacitors
14
arranged around a bit line contact
16
. Six container capacitors
14
are shown in
FIG. 2
, each of which has been labeled with separate reference designations A to F. Recall from
FIG. 1
that the bit lines of neighboring DRAM cells are electrically connected. To increase density, bit line contacts are shared by neighboring DRAM cells. In
FIG. 2
, the bit line contact
16
is shared by DRAM cells corresponding to container capacitors A and B. Not shown in
FIG. 2
are additional bit line contacts to the upper left, upper right, lower left and lower right of the illustrated bit line contact
16
. Container capacitors C, D, E and F are respectively associated with these additional bit line contacts.
To ensure that the neighboring container capacitors
14
remain isolated, it is necessary to maintain a minimum distance Dc, referred to herein as the minimum capacitor distance, between the outer layers
30
of separate container capacitors
14
. The minimum capacitor distance is the minimum distance by which neighboring capacitors must be separated so that effects such as bridging, punch-through and parasitic capacitance are prevented. The distance Dc is typically on the order of one thousand angstroms or less, and can be as small as several hundred angstroms. The actual distance is dependent upon the particular fabrication process and materials. Similarly, it is also necessary to maintain a minimum distance Db, referred to herein as the minimum bit line distance, between the outer layers
30
of each container capacitor
14
and the bit line contact
16
. The minimum bit line distance Db is illustrated by a circle
40
. The minimum bit line distance Db, which will often be different from the minimum capacitor distance Dc, is dependent upon alignment errors between the masks used to create the capacitor openings and the bit line contact openings as well as the effects mentioned in connection with the minimum capacitor distance Dc.
It is apparent from
FIG. 2
that only container capacitors A and B are at the minimum bit line distance Db. The other four container capacitors C, D, E and F are at distances slightly greater than the minimum bit line distance Db. It is also apparent from
FIG. 2
that each outer layer
30
of the container capacitors
14
is separated from the outer layer
30
of a neighboring container capacitor
30
at the minimum capacitor distance Dc at only one point on its perimeter—the point at which the transition from a flat top
14
a
or bottom wall
14
b
to a semi-circular side wall
14
c
occurs. The points at the minimum capacitor distance Dc are at the locations indicated by the vertical line segments Dc shown in FIG.
2
.
Because only one point on the perimeter of each of the oval-shaped container capacitors
14
is at the minimum capacitor distance Dc from each neighboring container capacitor
14
, and only two of the six container capacitors
14
are at the minimum bit line distance Db, it is apparent that valuable memory cell space, between the containers and the bit line contact is wasted. Although not illustrated, container capacitors with circular cross sections suffer from similar inefficiencies. Thus, known container capacitor shapes do not make efficient use of available space.
As memory cell density continues to increase, efficient use of space becomes ever more important. Therefore, what is needed is a container capacitor that makes more efficient use of available memory cell space.
SUMMARY OF THE INVENTION
The present invention provides an improved container capacitor with a pear-shaped cross section, as shown, for example, in FIG.
3
. The pear-shaped cross section has a larger perimeter, resulting in increased capacitor wall area and therefore increased capacitance, without decreasing the m

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