Enhanced bus connectivity through distributed loading

Details Enhanced bus connectivity through distributed loading Enhanced bus connectivity through distributed loading

1999-08-27

2003-10-21

Lefkowitz, Sumati (Department: 2833)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

Reexamination Certificate

active

06636920

ABSTRACT:

BACKGROUND
The invention relates generally to data processing systems and, more particularly, to methods and apparatuses for enhancing the electrical load bearing capacity of a bus for such systems.
Referring to
FIG. 1
, illustrative prior art computer system
100
utilizes Peripheral Component Interconnect (PCI) local bus
102
(controlled through bridge circuit
104
) to provide system expansion capability through, for example, PCI expansion slots
106
. The mechanical, electrical, and operational characteristics of the current 64-bit PCI local bus standard may be found in the “PCI Local Bus Specification” (revision 2.2, 1998), available from the PCI Special Interest Group in Portland, Oreg.
The PCI local bus specification was designed to provide a processor-independent interface to add-in boards, also commonly referred to as expansion cards or adapters. Because of signal integrity constraints, PCI bus
102
is typically limited in both data transfer rate and fan-out (number of adapter slots supported). The current 33 MHz 64-bit PCI architecture definition provides a peak data transfer rate of 264 megabytes per second (MB/s) and supports approximately 10 loads: one load attributable to bridge circuit
104
; one load attributable to a second bridge circuit (typically used to couple PCI local bus
102
to a secondary bus conforming to, for example, the Low Pin Count (LPC), Industry Standard Architecture (ISA) or Extended Industry Standard Architecture (EISA) standards); and 2 loads for each of 4 expansion slots
106
. Even more restrictive, in terms of expansion capability, is the current 66 MHz PCI architecture which is limited to approximately 6 loads (while providing a peak data transfer rate of 528 MB/s)—allowing only 2 expansion slots.
Referring to
FIG. 2
, 64-bit PCI local bus
102
generally couples bridge circuit
104
with one or more 32-bit PCI connectors
200
and one or more 64-bit connectors
202
(the total number of connectors limited by local bus
102
loading restrictions). As illustrated, lower address/data lines
204
(AD[
31
::
0
], C/BE[
3
::
0
]#, and PAR signal lines) interconnect bridge circuit
104
with both 32-bit and 64-bit connectors
200
and
202
respectively, while upper address/data lines
206
(AD[
63
::
32
], C/BE[
7
::
4
]#, PAR
64
, REQ
64
#, and ACK
64
# signal lines) interconnect bridge circuit
104
with 64-bit connectors
202
.
As shown in
FIG. 2
, lower address/data lines
204
are coupled to every PCI device on local bus
102
. It is common, however, for a computer system to have only 1 64-bit PCI device. This situation leads to a very unbalanced loading between the lower and upper address/data lines
204
and
206
respectively. This, in turn, limits the total number of PCI devices that may be coupled to computer system
100
. Thus, it would be beneficial to distribute the load of 32-bit and 64-bit expansion devices so as to provide increased expansion capability.
SUMMARY
The invention provides a technique for enhancing the electrical load bearing capacity of a computer system bus. In one embodiment, the bus comprises a 64-bit Peripheral Component Interconnect (PCI) bus having an additional set of control signals, wherein the additional set of control signals duplicate the standard PCI FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, and LOCK# signals. The duplicate set of control signals may be used to electrically decouple devices coupled to the original set of control signals from devices coupled to the duplicate set of control signals. In another embodiment, the invention provides a computer system having a bus as described above and a plurality of bus device connectors; some of the connectors are coupled to the original set of control signals and some of which are coupled to the duplicate set of control signals.


REFERENCES:
patent: 5761443 (1998-06-01), Kranich
patent: 5828865 (1998-10-01), Bell
patent: 5859989 (1999-01-01), Olarig et al.
patent: 6233632 (2001-05-01), Meiyappan et al.
patent: 6256689 (2001-07-01), Khosrowpour
PCI Specification Interest Group, “PCI LOCAL BUS SPECIFICATION,” Revision 2.2, pp. i-xx, 1-302, Dec. 18, 1998.

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