Enhanced built-in self-test circuit and method

Details Enhanced built-in self-test circuit and method Enhanced built-in self-test circuit and method

1997-02-14

1999-06-29

Palys, Joseph E.

Excavating

371 211, 371 225, G06F 1100

Patent

active

059180030

ABSTRACT:
An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.

REFERENCES:
patent: 4313200 (1982-01-01), Nishiura
patent: 4949341 (1990-08-01), Lopez et al.
patent: 5006787 (1991-04-01), Katirciog et al.
patent: 5075892 (1991-12-01), Choy
patent: 5113339 (1992-05-01), Woods et al.
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5146458 (1992-09-01), Ono
patent: 5151903 (1992-09-01), Mydill et al.
patent: 5173906 (1992-12-01), Dreibelbi et al.
patent: 5175836 (1992-12-01), Morgan
patent: 5224101 (1993-06-01), Popyack, Jr.
patent: 5301156 (1994-04-01), Talley
patent: 5301199 (1994-04-01), Ikenaga et al.
patent: 5309447 (1994-05-01), Moskowitz et al.
patent: 5375091 (1994-12-01), Berry, Jr. et al.
patent: 5412662 (1995-05-01), Honma et al.
patent: 5471482 (1995-11-01), Byers et al.
patent: 5490115 (1996-02-01), Shah et al.
patent: 5535164 (1996-07-01), Adams et al.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5640539 (1997-06-01), Goishi et al.

Affiliated with

Also associated with

Rating

Enhanced built-in self-test circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Enhanced built-in self-test circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced built-in self-test circuit and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1384427