Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2002-12-19
2004-12-07
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S713000, C257S712000
Reexamination Certificate
active
06828671
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for grounding an enhanced BGA package to an underlying heatsink.
(2) Description of the Prior Art
The semiconductor industry has for many years followed a path of product improvement by the electrically required approach of device miniaturization and by the therefrom following increase of the device packaging density. For many of the semiconductor devices, increased device density is implemented internally to the device by creating device features of smaller dimensions. Where these devices need to be assembled into complete device packages, the completed semiconductor devices are frequently assembled in multi-device packages. This has led to the field of high density interconnect technology, where multilayer structures are mounted on the surface of a substrate thereby connecting integrated circuits to one another. This approach results in high wiring and high packaging density, whereby many integrated circuit chips are physically and electrically interconnected and connected to a single substrate commonly referred to as a Multi-Chip-Module (MCM). Electrical device isolation is provided by layers of dielectric such as polyimide that separate various functional planes (such as signal lines, power lines and ground planes) in the substrate. Metal interconnects can readily be provided by metal lines that are embedded in other layers of dielectric, thereby using vias (holes) to provide electrical connections between the various types of lines. Interconnect lines must thereby be connected in such a manner that optimum performance can be realized for the completed package. For instance, adjacent layers must be formed such that primary signal propagation directions are orthogonal to each other. This to avoid crosstalk between lines that are in close physical proximity, which can induce false signals and noise between adjacent lines. Good planarity must also be maintained between adjacent layers of interconnect lines because the metal interconnect lines are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography. Patterned layers must therefore be substantially flat and smooth (i.e. have good planarity) so that these layers can serve as a base for the next layer.
One of the original approaches that has been used to create surface mounted, high pin count integrated circuit packages has been the use of Quad Flat Packs (QFP's) with various pin configurations. For QFP's, closely spaced leads along the four edges of the flat package are used for making electrical connections from where the electrical connections are distributed to the surrounding circuitry. The input/output (I/O) connections that can be made to QFP's are therefore confined to the edges of the flat package, which limits the number of I/O connections that can be made to the QFP even in applications where the pin to pin spacing is small. QFP's have found to be cost effective for semiconductor devices where the device I/O pin count does not exceed 200. To circumvent this limitation, a new package, a Ball Grid Array (BGA) package has been introduced. For the BGA package, the electrical contact points are distributed over the entire bottom surface of the package thereby eliminating the restriction of having I/O connects only around the periphery of the package. More contact points with greater spacing between the contact points can therefore be allocated across the BGA package than was the case with the QFP's. The contact points that are used for the BGA package are typically solder balls that have the added advantage of facilitating flow soldering of the package onto a printed circuit board.
A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier, such as a Printed Circuit Board (PCB). The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mils spacings in regular or staggered array patterns. The BGA package is part of a larger packaging approach that is often referred to as Chip Scale Packages (CSP), which is a packaging approach that is considered to be different from the previously highlighted approach of MCM's.
Flip Chip packages have in general been used to accommodate increased I/O count combined with increased high requirements for high performance IC's. Flip chip technology fabricates bumps (typically Pb/Sn solder) on Al pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. This approach can be applied to single-chip packaging and to higher integrated levels of packaging (in which the packages are larger) and to more sophisticated packaging media that accommodate several chips to form larger functional units.
Prior Art substrate packaging uses ceramic and plastic BGA packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years have seen the emergence of plastic BGA packaging; this packaging has become the main stream design and is frequently used in high volume BGA package fabrication. The plastic substrate BGA package performs satisfactorily when used for low-density flip-chip IC's. If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small, or if the chip power dissipation is high (in excess of 4 Watts per chip), the plastic structure becomes complicated and expensive.
It is therefore the objective of providing a package for flip chips that has a direct ground connect between the flip chip and a heatsink on the surface of which the flip chip is mounted. In a typical flip chip packaging arrangement, a substrate layer that contains three layers is used to connect the flip chip to surrounding circuitry, using wire bond connections between the flip chip and the substrate layer. The contact points of the BGA/flip chip make contact with contact points in the top surface of the substrate layer, the substrate layer re-distributes (fan-out) the BGA/flip-chip contact points. An opening is provided in each of the three layers that are contained in the substrate layer, this opening is filled with a low-resistivity material thus establishing electrical contact between one selected copper pad of the copper traces (in the upper layer of the substrate layer) and the heatsink. Connecting the ground point of the IC die to the selected copper pad of the copper traces completes the ground path between the ground of the IC die and the heatsink. A molding is encased between the lower surface of the BGA/flip-chip device and the upper surface of the substrate. This molding is referred to as underfill since it is filled in under the original BGA/flip-chip device. A heat sink is typically attached to the lower surface of the flip-chip.
FIG. 1
shows a Prior Art method of packaging a BGA/flip chip whereby a major part of the package contains a heatsink
10
. The semiconductor chip or die
12
takes up the center of the package; the contact points of die
10
are closely spaced around the periphery of the die
10
. Cavity
16
is provided in the heatsink
10
for the mounting of the Integrated Circuit (IC) chip
12
. Heatsink
10
has a surface that is electrically conductive. The top of the IC chip
12
is in close physical contact with the heatsink
10
via a thin adhesive layer
18
of thermally conductive epoxy that is deposited over the top surface of cavity
16
, the IC die
12
is attached to the heatsink
10
by means of this layer
18
. The adhesive layer
18
is cured after the IC die
12
has been inserted into cavity
16
. The contact points of the die
12
are conductive
Aquien Weddie
Briar John
Fee Setho Sing
ST Assembly Test Services PTE LTD
Zarneke David A.
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