Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-13
2003-06-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06581199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an engineering-change method of a semiconductor circuit at netlist changes after automatic placement and routing of a semiconductor circuit design.
2. Description of Related Art
FIG. 15
is a flowchart illustrating a conventional engineering-change method of a semiconductor circuit. In this figure, the reference numeral
1501
designates an original netlist. A P&R (placement and routing) process
1502
carries out placement and routing and logical optimization using the netlist
1501
, and changes the netlist to meet constraints such as timings. The P&R process produces a netlist
1503
and a layout
1504
. Subsequently, an ECO (Engineering Change Order) process
1505
carries out logical changes due to design problems and the like.
Here, the logical changes are sometimes made for the netlist
1501
when a layout engineer differs from a logic designer, or when it is difficult to read the netlist
1503
after the P&R process. The netlist produced by the logical changes of the netlist
1501
by the ECO process
1505
is a netlist
1506
.
Subsequently, a P&R process
1507
carries out the placement and routing and the logical optimization using the netlist
1506
, thereby making netlist changes to meet the constraints such as timings. The P&R process
1507
is the same as the P&R process
1502
, and produces a netlist
1508
and a layout
1509
that are changed.
With the foregoing configuration, the conventional engineering-change method of a semiconductor circuit has the following problems. When the original netlist
1501
is changed after the P&R process
1502
carries out the logical changes such as the logical optimization in an LSI design, it is necessary for the P&R process
1507
to perform logical optimization or logical changes according to a manual, thereby prolonging a design period.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide an engineering-change method of a semiconductor circuit capable of reducing the design period by making it possible to reflect logical changes in the design on a layout without making any design feedback even when a netlist is changed.
According to a first aspect of the present invention, there is provided an engineering-change method of a semiconductor circuit comprising: a placement and routing step of carrying out placement and routing and logical optimization using a first netlist to generate a second netlist and a first layout that undergo logical optimization; an engineering-change step of making logical changes in design for the first netlist to generate a third netlist; an engineering-change and formal verification step of conducting formal verification of the second netlist and the third netlist to generate a fourth netlist by changing the second netlist such that the fourth netlist becomes logically equivalent to the third netlist; and a layout generating step of generating a second layout by changing the first layout such that the second layout matches the fourth netlist.
According to a second aspect of the present invention, there is provided an engineering-change method of a semiconductor circuit comprising: a placement and routing step of carrying out placement and routing and logical optimization using a first netlist to generate a second netlist and a first layout that undergo logical optimization; an engineering-change step of making logical changes in design for the first netlist to generate a third netlist; and an engineering-change and formal verification/layout generating step of conducting formal verification of the second netlist and the third netlist to generate a fourth netlist by changing the second netlist such that the fourth netlist becomes logically equivalent to the third netlist, and of generating a second layout by changing the first layout such that the second layout matches the fourth netlist.
Here, the placement and routing step may generate the second netlist and the first layout such that they satisfy timing constraints or timing information including timing library information on each cell, and the engineering-change and formal verification step may generate the fourth netlist such that it satisfies the timing information.
The placement and routing step may generate the second netlist and the first layout such that they satisfy timing constraints or timing information including timing library information on each cell, and the engineering-change and formal verification/layout generating step may generate the fourth netlist such that it satisfies the timing information.
The placement and routing step may generate the second netlist and the first layout such that they satisfy crosstalk constraints or crosstalk information including crosstalk library information on each cell, and the engineering-change and formal verification step may generate the fourth netlist such that it satisfies the crosstalk information.
The placement and routing step may generate the second netlist and the first layout such that they satisfy crosstalk constraints or crosstalk information including crosstalk library information on each cell, and the engineering-change and formal verification/layout generating step may generate the fourth netlist such that it satisfies the crosstalk information.
The engineering-change method of a semiconductor circuit may further comprise a selection step of selecting, when the engineering-change and formal verification step generates a plurality of fourth netlists, one of the plurality of fourth netlists.
The engineering-change method of a semiconductor circuit may further comprise a selection step of selecting, when the engineering-change and formal verification/layout generating step generates a plurality of fourth netlists, one of the plurality of fourth netlists.
REFERENCES:
patent: 5754829 (1998-05-01), Motohiro et al.
patent: 5841674 (1998-11-01), Johannsen
patent: 5953236 (1999-09-01), Hossain et al.
patent: 5983376 (1999-11-01), Narayanan et al.
patent: 6014506 (2000-01-01), Hossain et al.
patent: 6226777 (2001-05-01), Zhang
patent: 2002/0162086 (2002-10-01), Morgan
patent: 10-269256 (1998-10-01), None
patent: 2000-003382 (2000-01-01), None
patent: 2000-242675 (2000-09-01), None
Lin Sun James
Mitsubishi Denki & Kabushiki Kaisha
Siek Vuthe
LandOfFree
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