Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-04-15
2008-04-15
Lee, Christopher E. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S309000, C711S118000, C712S032000
Reexamination Certificate
active
07360008
ABSTRACT:
The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.
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Cai Zhong-Ning
Liu Yen-Cheng
Sistla Krishnakanth V.
Intel Corporation
Lee Christopher E.
McAbee David P.
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