Enforcement of cache coherency policies using process...

Details Enforcement of cache coherency policies using process... Enforcement of cache coherency policies using process...

2011-01-25

2011-01-25

Portka, Gary J (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C710S200000, C711S152000, C713S375000

Reexamination Certificate

active

07877549

ABSTRACT:
In general, this disclosure describes techniques of ensuring cache coherency in a multi-processor computing system. More specifically, a relaxed coherency mechanism is described that provides the appearance of strong coherency and consistency to correctly written software executing on the multi-processor system. The techniques, as described herein, combine software synchronization instructions with certain hardware-implemented instructions to ensure cache coherency.

REFERENCES:
patent: 6049866 (2000-04-01), Earl
patent: 6745294 (2004-06-01), Wilson et al.
patent: 6950913 (2005-09-01), Glasco
patent: 7103631 (2006-09-01), van der Veen
patent: 7194587 (2007-03-01), McCalpin et al.
Kuo et al., “MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing”, High-Performance Computer Architecture, Jan. 1999 (article—5 pages).
Kuo et al., “MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing”, High-Performance Computer Architecture, Jan. 1999 (citation—1 page).

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