Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-10-06
2001-10-16
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S198000, C365S207000
Reexamination Certificate
active
06304506
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89119721, filed Sep. 25, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an energy-saving device for a memory circuit. More particularly, the present invention relates to an energy-saving device capable of turning off the power to the second sense amplifier inside a memory circuit immediately after data transmission.
2. Description of Related Art
FIG. 1
is a diagram showing a conventional memory circuit. As shown in
FIG. 1
, the memory circuit includes a first sense amplifier
10
, a second sense amplifier
12
and an input/output buffer
14
. The first sense amplifier
10
sends out two different types of signals NL and NDL to the second sense amplifier
12
. After some data processing activities inside the second sense amplifier
12
, the data are transmitted to the input/output buffer
14
for output.
The second sense amplifier
12
is triggered by a local sense amplifier enable (LSAE) signal acting through the gate terminals of the NMOS transistors
16
,
18
and
20
. Since the output terminal of an inverter
22
inside the input/output buffer
14
is connected to the input terminal of another inverter
24
and vice versa, signal transmitted to the input/output buffer
14
can be retained. Hence, the second sense amplifier
12
must remain active for a definite period before it can be shut off after data transmission has stopped. Because the second sense amplifier
12
includes a plurality of MOS transistors inside, considerable current flows inside the second sense amplifier
12
and hence energy consumption is high.
Although the setting of a delay chain to control the opening and shutting down of the sense amplifier has been proposed to save energy , such a method is constrained by the manufacturing process as well as temperature variations. Consequently, proper timing control of the sense amplifier is very difficult leading to extra power consumption or failures.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an energy-saving device for a memory circuit such that power to a sense amplifier inside the memory circuit is shut off immediately at the end of data transmission. Hence, wasting of energy by the memory circuit is prevented. Moreover, the energy-saving device is immune to temperature and processing variations.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an energy-saving device for a memory circuit. The energy-saving device is capable of immediately terminating a local sense amplifier enable (LSAE) signal to a sense amplifier circuit. The sense amplifier includes a plurality of different operational signals and a plurality of different inverse operational signals.
The energy-saving device comprises a plurality of Schmitt triggering circuits, a plurality of data-transmission testers, a data-transmission-testing pulse-generation circuit and a power shut down signaling circuit.
Each Schmitt triggering circuit receives an operational signal and an inverse operational signal and then outputs a corresponding Schmitt triggering signal. Each data transmission tester is connected to a Schmitt triggering circuit. When a Schmitt triggering signal is received, the data-transmission tester will issue a response signal. The data transmission testers are connected to the data-transmission-testing pulse-generation circuit. When the data-transmission-testing pulse-generation circuit receives a response signal from any one of the data transmission testers, a data-transition-detected pulse is issued. The power shut down signaling circuit is connected to the data-transmission-testing pulse-generation circuit. On receiving a data-transition-detected pulse, the power shut down signaling circuit will immediately terminate the local sense amplifier enable (LSAE) signal.
In this invention, Schmitt triggering circuits and data transmission testers are used. Since the circuits have some internal magnetic hysteresis, shut down will occur only after a definite interval. Hence, erroneous decisions due to impulses are prevented.
The data-transmission-testing pulse-generation circuit further includes a plurality of NMOS transistors, a first inverter, a NOR gate, an invert-delay device, a PMOS transistor and a second inverter. The gate terminals of the NMOS transistors are connected to the respective data transmission testers for receiving a response signal. All the source terminals of the NMOS transistors are connected to a low voltage. The input terminal of the inverter is connected to a low voltage and the output terminal of the inverter is connected to the drain terminal of the NMOS transistor. The NOR gate has a first input terminal, a second input terminal and an output terminal. The first input terminal of the NOR gate is connected to the output terminal of the first inverter and the second input terminal of the NOR gate is connected to the input terminal of the first inverter. The invert-delay device comprises an odd number of inverters serially connected together. The input terminal of the invert-delay device is connected to the output terminal of the NOR gate. The gate terminal of the PMOS transistor is connected to the output terminal of the invert-delay circuit. The input terminal of the second inverter is connected to the output terminal of the first inverter and the output terminal of the second inverter is used for issuing a data-transition-detected pulse. The low voltage can be an earth connection, for example.
The power shut down signaling circuit includes a first NAND gate, a first inverter, a first PMOS transistor, a first NMOS transistor, a second inverter, a third inverter, a NOR gate, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a second NAND gate and an eighth inverter. The first NAND gate has two input terminals for receiving the data-transition-detected pulse and the local sense amplifier enable (LSAE) signal. The first inverter receives a global sense amplifier enable (GSAE) signal. The source terminal of the first PMOS transistor is connected to a high voltage and the gate terminal of the first PMOS transistor is connected to the output terminal of the first NAND gate. The drain terminal of the first NMOS transistor is connected to the drain terminal of the first PMOS transistor. The gate terminal of the first NMOS transistor is connected to the first inverter. The source terminal of the first NMOS transistor is connected to a low voltage. The input terminal of the second inverter is connected to the drain terminal of the first NMOS transistor. The input terminal of the third inverter is connected to the output terminal of the second inverter and the output terminal of the third inverter is connected to the input terminal of the second inverter. The NOR gate has two input terminals for receiving the data-transition-detected pulse and signal from the input terminal of the second inverter. The gate terminal of the second PMOS transistor receives the global sense amplifier enable (GSAE) signal. The source terminal of the second PMOS transistor is connected to a high voltage. The gate terminal of the second NMOS transistor is connected to the output terminal of the NOR gate and the drain terminal of the second NMOS transistor is connected to the drain terminal of the second PMOS transistor. The gate terminal of the third NMOS transistor receives the GSAE signal. The drain terminal of the third NMOS transistor is connected to the source terminal of the second PMOS transistor and the source terminal of the third NMOS transistor is connected to a low voltage. The input terminal of the fourth inverter is connected to the drain terminal of the second NMOS transistor. The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter an
Huang Shih-Huang
Lu Hsin-Pang
Ho Hoai V.
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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