Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-03-21
2003-05-20
Dharia, Rupal (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S065000, C711S201000
Reexamination Certificate
active
06567884
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices generally and, more particularly, to an endian-controlled counter for single/multi synchronous port(s) with bus matching.
BACKGROUND OF THE INVENTION
Bus matching generally involves converting data from one format to another (e.g., x
36
(long word), x
18
(word) or x
9
(byte)) in order to be transferred through a fixed bus width. Bus matching facilitates a single bus servicing multiple memory configurations. Bus matching was previously available only for FIFO applications.
Conventional methods of bus matching implement an auxiliary register to store the unused portion of the long-word. Auxiliary registers are effective at bus matching but also have several disadvantages. Auxiliary registers (i) use up additional processor time after data is fetched, time allotted to execute the instruction cycles necessary for subsequent byte manipulation, (ii) require the use of complex and/or expensive circuitry to process the long-word data after the data is made available externally in the internal format, and/or (iii) require unnecessary auxiliary internal storage registers which increase power consumption and area allocation for the endian manipulation circuitry.
In order to manage the handling of both endian standards, conventional methods have included:
a) byte-swapping devices which selectively swap the bytes (e.g., x
9
) of data transferred (usually between a processor and the storage device), controlled by addresses provided.by the processor;
b) memory managers to receive lines of data from the memory based on the specific endian mode of operation;
c) data processing devices that receive one or more bytes of data in parallel from the memory, and are able to perform manipulation of the bytes of data, usually making use of a bit reversing circuit and a word reversing circuit;
d) manipulation of the two LSBs of the access address to change pointer values, and thus point to the correct sub-word data;
e) computer program-products (i.e., software implementation), that take the contents of a register and operate on the two LSBs of the byte address to generate a new byte address that corresponds with another architecture;
f) converters for assembling data stored in a register according to endian formats stored in a second register; and/or
g) auxiliary registers to store the unused portion of the long-word, during a specific clock cycle, for specific manipulation during subsequent clock cycles.
Conventional methods for manipulating a long word are less than adequate. Additional time is required after fetching a long word either through specific hardware or through software manipulation routines (e.g., additional processor time allotted to execute the instruction cycles). Complex and expensive circuitry is used to process the long-word data after it, is made available externally. Auxiliary internal storage registers increase the power consumption and area allocation for the endian-manipulation circuitry.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory, a first circuit and a second circuit. The memory may be configured to read and/or write data to/from one or more ports. The first circuit may be configured to transfer data between an external I/O bus and an internal I/O bus in response to a plurality of control signals. The second circuit may be configured to generate the plurality of control signals in response to a plurality of input signals. The data signals generated by the two circuits may allow reduced bus size access in one or more word formats.
The objects, features and advantages of the present invention include providing a circuit, architecture, and method for (i) matching a bus width in a memory, (ii) implementing data transfer in one or more word formats and/or (iii) implementing the bus matching and/or data transfer in a single/multi port memory.
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CMOS Bus-Matching SyncFIFO™ 256×36, 512×36, 1,024×36; Preliminary IDT723623, IDT723633, IDT723643; Integrated Device Technology, Inc.; May 1998; pp. 1-28.
Cypress Semiconductor Corp.
Dharia Rupal
Maiorana P.C. Christopher P.
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