Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-05-24
2009-06-30
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C708S233000
Reexamination Certificate
active
07555692
ABSTRACT:
A processor that protects an execution pipeline includes a residue-based error detection infrastructure including a first logic for computing a first residue of a result of an executed instruction instance, and a second logic for computing a second residue of the result. The second logic applies arithmetic operations of the executed instruction instance to residues of operands of the instruction instance. The execution pipeline includes registers and one or more arithmetic execution units. A method of protecting an execution pipeline includes performing one or more operations of an instruction instance on residues of operands of the instruction instance, computing a first residue of a result of the operations on the operand residues, computing a second residue from a result of executing the instruction instance, and checking the first residue against the second residue to determine whether errors were introduced while the instruction instance was resident in the execution pipeline.
REFERENCES:
patent: 4870607 (1989-09-01), Ishizuka
patent: 6519730 (2003-02-01), Ando et al.
U.S. Appl. No. 11/145,397, filed Jun. 3, 2005, and naming as inventor(s) Sorin Iacobovici.
U.S. Appl. No. 11/209,124, filed Aug. 22, 2005, and naming as inventor(s) Sorin Iacobovici.
Lamarre Guy J
Osha • Liang LLP
Sun Microsystems Inc.
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