Abrading – Precision device or process - or with condition responsive... – By optical sensor
Reexamination Certificate
2000-06-30
2002-04-23
Rose, Robert A. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
By optical sensor
C451S008000
Reexamination Certificate
active
06375540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the chemical mechanical polishing (CMP) of semiconductor wafers, and more particularly, to techniques for polishing end-point detection.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired fictional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level there is a need to planarize metal or associated dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization, e.g., such as copper.
In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to scrub, buff, and polish a wafer. Slurry is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CNP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
FIG. 1A
shows a cross sectional view of a dielectric layer
102
undergoing a fabrication process that is common in constructing damascene and dual damascene interconnect metallization lines. The dielectric layer
102
has a diffusion barrier layer
104
deposited over the etch-patterned surface of the dielectric layer
102
. The diffusion barrier layer, as is well known, is typically titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination of tantalum nitride (TaN) and tantalum (Ta). Once the diffusion barrier layer
104
has been deposited to the desired thickness, a copper layer
104
is formed over the diffusion barrier layer in a way that fills the etched features in the dielectric layer
102
. Some excessive diffusion barrier and metallization material is also inevitably deposited over the field areas. In order to remove these overburden materials and to define the desired interconnect metallization lines and associated vias (not shown), a chemical mechanical planarization (CMP) operation is performed.
As mentioned above, the CMP operation is designed to remove the top metallization material from over the dielectric layer
102
. For instance, as shown in
FIG. 1B
, the overburden portion of the copper layer
106
and the diffusion barrier layer
104
have been removed. As is common in CMP operations, the CMP operation must continue until all of the overburden metallization and diffusion barrier material
104
is removed from over the dielectric layer
102
. However, in order to ensure that all the diffusion barrier layer
104
is removed from over the dielectric layer
102
, there needs to be a way of monitoring the process state and the state of the wafer surface during its CMP processing. This is commonly referred to as end-point detection. In multi-step CMP operations there is a need to ascertain multiple end-points (e.g., such as to ensure that Cu is removed from over the diffusion barrier layer; and to ensure that the diffusion barrier layer is removed from over the dielectric layer). Thus, end-point detection techniques are used to ensure that all of the desired overburden material is removed. A common problem with current end-point detection techniques is that some degree of over-etching is required to ensure that all of the conductive material (e.g., metallization material or diffusion barrier layer
104
) is removed from over the dielectric layer
102
to prevent inadvertent electrical interconnection between metallization lines. A side effect of improper end-point detection or over-polishing is that dishing
108
occurs over the metallization layer that is desired to remain within the dielectric layer
102
. The dishing effect essentially removes more metallization material than desired and leaves a dish-like feature over the metallization lines. Dishing is known to impact the performance of the interconnect metallization lines in a negative way, and too much dishing can cause a desired integrated circuit to fail for its intended purpose.
FIG. 1C
shows a prior art belt CMP system in which a pad
150
is designed to rotate around rollers
151
. As is common in belt CMP systems, a platen
154
is positioned under the pad
150
to provide a surface onto which a wafer will be applied using a carrier
152
as shown in FIG.
113
. One way of performing end-point detection is to use an optical detector
160
in which light is applied through the platen
154
, through the pad
150
and onto the surface of the wafer
100
being polished. In order to accomplish optical end-point detection, a pad slot
150
a
is formed into the pad
150
. In some embodiments, the pad
150
may include a number of pad slots
150
a
strategically placed in different locations of the pad
150
. Typically, the pad slots
150
a
are designed small enough to minimize the impact on the polishing operation. In addition to the pad slot
150
a
, a platen slot
154
a
is defined in the platen
154
. The platen slot
154
a
is designed to allow the optical beam to be passed through the platen
154
, through the pad
150
, and onto the desired surface of the wafer
100
during polishing.
By using the optical detector
160
, it is possible to ascertain a level of removal of certain films from the wafer surface. This detection technique is designed to measure the thickness of the film by inspecting the interference patterns received by the optical detector
160
. Although optical end-point detection is suitable for some applications, optical end-point detection may not be adequate in cases where end-point detection is desired for different regions or zones of the semiconductor wafer
100
. In order to inspect different zones of the wafer
100
, it is necessary to define several pad slots
150
a
as well as several platen slots
154
a
. As more slots are defined in the pad
150
and the platen
154
, there may be a greater detrimental impact upon the polishing being performed on the wafer
100
. That is, the surface of the pad
150
will be altered due to the number of slots formed into the pad
150
as well as complicating the design of the platen
154
.
Additionally, conventional platens
154
are designed to strategically apply certain degrees of back pressure to the pad
150
to enable precision removal of the layers from the wafer
100
. As more platen slots
154
a
are defined into the platen
154
, it will be more difficult to design and implement pressure applying platens
154
. Accordingly, optical end-point detection is generally complex to integrate into a belt CMP system and also poses problems in the complete detection of end-point throughout different zones or regions of a wafer without impacting the CMP system's ability to precision polish layers of the wafer.
FIG. 2A
shows a partial cross-sectional view of an exemplary semiconductor chip
201
after the top layer has undergone a copper CMP process. Using standard impurity implantation, photolithography, and etching techniques, P-type transistors and N-type transistors are fabricated into the P-type silicon substr
Gotkis Yehiel
Mikhaylich Katrina A.
Ravkin Mike
Lam Research Corporation
Martine & Penilla LLP
Rose Robert A.
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