Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-05-09
2003-06-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
Reexamination Certificate
active
06573188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming patterned silicon layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced process control, patterned silicon layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic layer dimensions have decreased, it has become increasingly more difficult in the art of microelectronic fabrication to form within microelectronic fabrication patterned microelectronic layers with enhanced process control.
It is thus desirable in the art of microelectronic fabrication to form within microelectronic fabrications patterned microelectronic layers with enhanced process control.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming, with desirable properties within microelectronic fabrications, patterned microelectronic layers.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Poulsen et al., in U.S. Pat. No. 4,528,438 (a plasma etch method for forming within a microelectronic fabrication a patterned microelectronic layer with enhanced endpoint detection, by employing within the plasma etch method an emission spectroscopy endpoint detection method) ; (2) Yu et al., in U.S. Pat. No. 5,747,380 (a plasma etch method for forming within a microelectronic fabrication a patterned microelectronic layer with enhanced endpoint detection by employing within a substrate which is etched within the plasma etch method dummy features such as to enhance within the plasma etch method optical emission endpoint detection); and (3) Zheng, in U.S. Pat. No. 6,306,755 (another plasma etch method for forming within a microelectronic fabrication a patterned microelectronic layer with enhanced endpoint detection by employing within a substrate which is etched within the plasma etch method dummy features such as to enhance within the plasma etch method optical emission endpoint detection).
Desirable in the art of microelectronic fabrication are additional methods and materials through which there may be formed within microelectronic fabrications patterned microelectronic layers with enhanced process control.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming a patterned microelectronic layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the patterned microelectronic layer is formed with enhanced process control.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a patterned silicon layer within a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate having formed thereover a first silicon layer selected from the group consisting of amorphous silicon layers, polycrystalline silicon layers, monocrystalline silicon layers and germanium alloy layers thereof. Within the present invention, the first silicon layer has a first region laterally adjacent a second region. There is then formed over the first region of the first silicon layer but not over the second region of the first silicon layer an etch detection layer. There is then formed over the first region of the first silicon layer, the second region of the first silicon layer and the etch detection layer, and contacting both the etch detection layer and the second region of the first silicon layer, a second silicon layer selected from the group consisting of amorphous silicon layers, polycrystalline silicon layers, monocrystalline silicon layers and germanium alloy layers thereof. There is then formed over the second silicon layer a masking layer which defines: (1) a first aperture over the first region of the first silicon layer and the etch detection layer; and (2) a second aperture over the second region of the first silicon layer. Finally, there is then etched simultaneously the second silicon layer within the first aperture and the second aperture while employing the etch detection layer as an endpoint detection layer such as to substantially completely etch within the second region the second silicon layer but insubstantially etch within the second region the first silicon layer. Alternatively phrased, the invention provides for forming over a substrate a first silicon layer having formed thereover a second silicon layer, where an etch detection layer is formed interposed between a first region of the first silicon layer and the second silicon layer but not an adjacent second region of the first silicon layer and the second silicon layer. The etch detection layer provides a means for etch process control such as to substantially completely etch the second silicon layer within the second region, but insubstantially etch the first silicon layer within the second region.
The present invention provides a method for forming a patterned microelectronic layer within a microelectronic fabrication, wherein the patterned microelectronic layer is formed with enhanced process control.
The present invention realizes the foregoing object by employing when forming a patterned second silicon layer upon a first silicon layer within a microelectronic fabrication an etch detection layer interposed between a first region of a second silicon layer and the first silicon layer, but not a second region of the second silicon layer and the first silicon layer, such that when simultaneously etching the second silicon layer within a first aperture and a second aperture defined by a patterned masking layer formed over the first region and the second region while employing the etch detection layer as an endpoint detection layer there may be substantially completely etched within the second region the second silicon layer but insubstantially etched within the second region the first silicon layer. Alternatively phrased, the invention provides for forming over a substrate a first silicon layer having formed thereover a second silicon layer, where an etch detection layer is formed interposed between a first region of the first silicon layer and the second silicon layer but not an adjacent second region of the first silicon layer and the second silicon layer. The etch detection layer provides a means for etch process control such as to substantially completely etch the second silicon layer within the second region, but insubstantially etch the first silicon layer within the second region.
REFERENCES:
patent: 4528438 (1985-07-01), Poulsen et al.
patent: 5747380 (1998-05-01), Yu et al.
patent: 6306755 (2001-10-01), Zheng
Lai Tsung-Mu
Tseng Wan-Sheng
Wu Hua-Shu
Le Thao P.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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