Electrical computers and digital processing systems: support – Data processing protection using cryptography
Patent
1998-02-27
2000-07-11
Peeso, Thomas R.
Electrical computers and digital processing systems: support
Data processing protection using cryptography
713190, 713193, 713201, 380 28, 380 33, 380 52, H04L 900
Patent
active
060888008
ABSTRACT:
An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
REFERENCES:
patent: 3098153 (1963-07-01), Heijn
patent: 4809169 (1989-02-01), Sfarti et al.
patent: 4922418 (1990-05-01), Dolecek
patent: 5038282 (1991-08-01), Gilbert et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5301340 (1994-04-01), Cook
patent: 5343416 (1994-08-01), Eisig et al.
patent: 5475856 (1995-12-01), Kogge
patent: 5524250 (1996-06-01), Chesson et al.
patent: 5546343 (1996-08-01), Elliott et al.
patent: 5627966 (1997-05-01), Hanko
patent: 5636351 (1997-06-01), Lee
patent: 5694143 (1997-12-01), Fielder et al.
patent: 5708836 (1998-01-01), Wilkinson et al.
patent: 5724422 (1998-03-01), Shang et al.
patent: 5864683 (1999-01-01), Boebert et al.
patent: 5926546 (1999-07-01), Maeda et al.
patent: 5987124 (1999-11-01), Matyas, Jr. et al.
Barrett, Paul, "Implementing The Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor," Computer Security LTD, Aug. 1986, pp 311-323.
Montgomery, Peter L., "Modular Multiplication Without Trial Division," Mathematics of Computation, vol. 44, No. 170, Apr. 1985, pp 519-521.
Jones, D. et al., "A Time-Multiplexed FPGA Architecture for Logic Emulation," Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, May 1995, pp 495-498.
Mirsky, Ethan et al., "Matrix: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," IEEE Symposium on FPGA's For Custom Computing Machines, Published at FCCM '96, Apr. 17-19, 1996, pp 1-10.
Chen, Dev C., "A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths," IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp 1895-1904.
Yeung, Alfred K. et al., "A 2.4GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP," IEEE International Solid-State Circuits Conference, ISSCC95, Feb. 16, 1995, Session 6, Digital Design Elements, Paper TA 6.3, 3 pages.
Wolter, Stefan et al., "On the VLSI Implementation of the International Data Encryption Algorithm IDEA," IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, Apr. 30-May 3, 1995., vol. 1, Apr. 30, 1995, pp 397-400.
Sauerbrey, J., "A Modular Exponentiation Unit Based on Systolic Arrays," Advances in Cryptology--Auscrpyt, Gold Coast, Queensland, Dec. 13-16, 1992, conf. 3, Dec. 13, 1992, pp 505-516.
Jones David E.
O'Connell Cormac M.
Mosaid Technologies Incorporated
Peeso Thomas R.
LandOfFree
Encryption processor with shared memory interconnect does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Encryption processor with shared memory interconnect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Encryption processor with shared memory interconnect will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-553134