Encryption-based security protection for processors

Details Encryption-based security protection for processors Encryption-based security protection for processors

2006-02-07

2006-02-07

Peeso, Thomas R. (Department: 2132)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

C713S152000

Reexamination Certificate

active

06996725

ABSTRACT:
Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).

REFERENCES:
patent: 3573747 (1971-04-01), Adams et al.
patent: 3609697 (1971-09-01), Blevins et al.
patent: 3798360 (1974-03-01), Feistel
Product Bulletin entitled, “VMS320 High Speed PCMCIA Security Tokken Crytographic Engine”, by VLSI Technology, Inc., 1997, PB-0497-020, (pp. 6).

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