Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-07-01
1998-05-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711124, 711145, G06F 1208
Patent
active
057522588
ABSTRACT:
A directory system directs cache line access requests from processors in a multi-processor system with a shared memory system through a cache line states directory. The cache line states directory stores a state value that identifies a cache line shared states word. The cache line shared states word identifies the processor that owns the cache line and the state of access of each processor that shares access to the cache line. A state value encoder encodes a cache line shared state word into a state value and loads the state value into the cache line states directory. A state value decoder decodes the state value into a cache line shared state word for use by the cache line directory system in retrieving the cache line. A plurality of cache line tables are used with each cache line assigned to one of the tables. The cache line table stores a state value for each cache line shared states word stored in the table. The encoder and decoder perform a table look-up to convert between a cache line shared state word and a state value. Each of said cache line tables stores an ordered list of cache line shared state words and their corresponding state values. The ordered list is a list of cache line shared state words that have the most significance to the multi-processor system.
REFERENCES:
patent: 5230070 (1993-07-01), Liu
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5426754 (1995-06-01), Grice et al.
Bromley Mark
Guzovskiy Aleksandr
Zak, Jr. Robert C.
Bragdon Reginald G.
Chan Eddie P.
Knearl Homer L.
Kubida William J.
Sun Microsystems Inc.
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