Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-09-05
2006-09-05
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189050, C365S203000
Reexamination Certificate
active
07102942
ABSTRACT:
An encoding circuit for a semiconductor apparatus and a redundancy control circuit using the same, in which a multiplicity of external signals are coupled to a precharge node in common to output a predetermined encoding signal. According to the encoding circuit, it is possible to reduce an area occupied by the encoding circuit and advantageously to prevent a time delay effect from the supply of the external signals to the generation of the encoding signal. Further, it is possible to lessen the generation of glitch signals due to delays in generating global redundancy signals of a redundancy circuit, so that the performance of the semiconductor apparatus can be improved.
REFERENCES:
patent: 5920515 (1999-07-01), Shaik et al.
patent: 6094381 (2000-07-01), Isa
patent: 6292408 (2001-09-01), Kawashima et al.
patent: 6441676 (2002-08-01), Koehl et al.
patent: 6972599 (2005-12-01), Forbes
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nguyen N
Phung Anh
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