Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-07-08
2008-07-08
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S768000
Reexamination Certificate
active
07398449
ABSTRACT:
A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
REFERENCES:
patent: 4672609 (1987-06-01), Humphrey et al.
patent: 4713816 (1987-12-01), Van Gils
patent: 5226043 (1993-07-01), Pughe et al.
patent: 5291498 (1994-03-01), Jackson et al.
patent: 5691996 (1997-11-01), Chen et al.
patent: 5751744 (1998-05-01), Babb
patent: 5761221 (1998-06-01), Baat et al.
patent: 5768294 (1998-06-01), Chen et al.
patent: 5917838 (1999-06-01), Wardrop
patent: 6044483 (2000-03-01), Chen et al.
patent: 6125467 (2000-09-01), Dixon
patent: 6574774 (2003-06-01), Vasiliev
patent: 6732291 (2004-05-01), Kilmer et al.
patent: 2005/0081085 (2005-04-01), Ellis et al.
P. Koopman and T. Chakravarty, “Cyclic Redundancy Code (CRC) Polynomial Selection for Embedded Networks”,Int'lConf. On Dependable Sys. and Networks., DSN-2004, pp. 1-10, 2004.
S. Kaneda and E. Fujiwara, “Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems”,IEEE Trans. Computers, vol. C-31, No. 7, pp. 596-602, Jul. 1982.
M. Hamada and E. Fujiwara, “A Class of Error Control Codes for Byte Organized Memory Systems—SbEC-(Sb+S)ED Codes”,IEEE Trans. Computers, vol. 46, No. 1, pp. 105-109, Jan. 1997.
Hathaway Robert G.
Normoyle Kevin B.
Auvinen Stuart T.
Azul Systems, Inc.
gPatent LLC
Torres Joseph D
LandOfFree
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