Encoder/decoder system with suppressed error propagation

Details Encoder/decoder system with suppressed error propagation Encoder/decoder system with suppressed error propagation

1998-01-20

2000-08-01

Tokar, Michael

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

341 59, H03M 500, H03M 700

Patent

active

06097320&

ABSTRACT:
A magnetic recording system with a rate 16/17(0,6/8) encoder/decoder modulation code. This modulation code has a low k constraint for synchronization of a road clock of the magnetic recording system. Furthermore, this magnetic recording system has a low hard error rate due to low 3- and 4-byte error propagation. The digital logic circuit for the encoder/decoder system is elegantly simple. Such simplicity reduces propagational delays and circuit size, as measured in number of logic gates. The modulation code is implemented with a decoder that includes a lower byte decoder and an upper byte decoder. An input of the upper byte decoder is in part coupled to and in part decoupled from the lower byte decoder. Similarly, an input of the lower byte decoder is in part coupled to and in part decoupled from the upper byte decoder.

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IBM Technical Disclosure Bulletin, "Rate 16/17 (0,6/6) Code," vol. 31, No. 8, Jan. 1989.
Silicon Systems, A Texas Instruments Company, SSI 32P4101 "EPRML Read Channel w/15/17's, ENDEC, 4-Burst Servo (A,B,C,D) Prototype," Mar. 6, 1997 .

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