Encoder and decoder circuits for dynamic bus

Details Encoder and decoder circuits for dynamic bus Encoder and decoder circuits for dynamic bus

2006-12-26

2006-12-26

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S093000, C326S105000, C710S110000, C365S205000

Reexamination Certificate

active

07154300

ABSTRACT:
A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

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