Encasing arrangement for a semiconductor component

Details Encasing arrangement for a semiconductor component Encasing arrangement for a semiconductor component

2007-04-24

2007-04-24

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Housing or package filled with solid or liquid electrically...

C257S729000, C257S730000, C257S773000, C257S776000, C257S779000, C257S782000, C257S783000

Reexamination Certificate

active

10149892

ABSTRACT:
A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.

REFERENCES:
patent: 5708567 (1998-01-01), Shim et al.
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 5843810 (1998-12-01), Sato et al.
patent: 5905633 (1999-05-01), Shim et al.
patent: 6433412 (2002-08-01), Ando et al.
patent: 2001/0040299 (2001-11-01), Moden
patent: 10 065 072 (1998-03-01), None
Andros, F. et al.: “TBGA Package Technology”, IEEE, vol. 17, No. 4, Nov. 1994, pp. 564-568.
Author not listed: “Thermische Modellierung von Ball Grid Arrays”, [Thermal Simulation of Ball Grid Arrays], Elektronik, Aug. 1997, pp. 142-144.
Beine, H.: “Mikro-BGA: Durchbruch für die Chip-Scale-Packages”, [Micro-BGA: Breakthrough for the Chip-Scale-Packages], productronic, Nov., 1997, pp. 124-125.
Moscicki, J.-P.: “CSP-BGA Gehäuse: Die Kleinste der Kleinen”, [CSP-BGA Casing: The Smallest of the Small], Elektronik, Dec., 1998, pp. 58-61.
Eyman, L. et al.: “A Thermally Enhanced 2-Layer PBGA Substrate Design”, Motorola Inc., Jan. 1999.

Affiliated with

Also associated with

Rating

Encasing arrangement for a semiconductor component does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Encasing arrangement for a semiconductor component, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Encasing arrangement for a semiconductor component will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3796776