Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-09
2002-11-05
Smith, Matthew (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C717S108000
Reexamination Certificate
active
06477698
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to increasing the granularity of the behavior level of Hardware Description Languages (HDL). The invention results in extending the usefulness of applications that use HDL behavior level descriptions to define the design, but require a finer level of granularity to perform the required task. More specifically, this invention relates to a system and method for transforming the integrated processes within the HDL behavior description to independent HDL objects.
BACKGROUND OF THE INVENTION
HDL is an acronym for Hardware Description Language. HDLs provide the means of specifying a digital system or design at various levels of abstraction. HDLs have evolved into two standards: Verilog and VHDL. The terms “design” and “digital system” are used interchangeably throughout this description. An HDL behavioral description is an abstraction of how a digital system works described with HDL in the following manner: the function of the digital system is described in terms of its inputs but no effort is made to describe how the digital system is implemented in terms of logic gates. An HDL process is the basic essence of the HDL behavioral description. A process can be thought of as independent concurrent thread of control. HDL processes are integral part of HDL module/entity (refer to the definition of HDL module/entity bellow). An HDL module or entity is a self-contained block of HDL descriptions that can reused through instantiation. HDL modules/entities contain processes and instantiations of other modules/entities. HDL module corresponds to the definition of module in the Verilog HDL. HDL entity corresponds to the definition of entity in the VHDL HDL. The terms HDL module and HDL entity are used interchangeably throughout this description. An HDL gate is an HDL module/entity which describes a generic logic function or technology specific logic function. An HDL object is a self-contained independent block within the HDL description that can be reused through instantiation. HDL objects can be defined explicitly and implicitly. Explicit HDL objects are formally defined within the HDL description. Examples of explicit HDL objects are HDL module/entities and HDL gates. Implicit HDL objects are described in a non-HDL (HDL tool specific) format or implied through the internal data structure of a HDL tool.
Structural gate level description is the representation of the design in terms logic gates or technology specific components. This representation can be described using HDLs or specific formats such as EDIF, XNF. Typically, the structural gate level description is the output of the synthesis process (which is the process of transforming HDL Behavioral description into a structural gate level description). Partitioning is the process of distribution of logic amongst multiple devices. Typically, the distribution process must comply with a set of constraints characteristic of the devices. For example, in case of partitioning into multiple FPGA devices, the partitioning process must meet the logic capacity and I/O limits of the FPGA devices. Floorplanning is the process of placement or arrangement of logic within a device to achieve a desired performance goal. For example, in case of floorplanning an FPGA device, the goal of the placement of logic is such that the clock speed of the design implemented in the FPGA device is increased and/or the route time of the FPGA device is reduced. For structural gate level description, logic size means the amount of logic resources used to implement a logic function (where the logic resources can be generic (technology independent) logic gates or technology specific components) and granularity means the average logic size of the objects used in the description of a design (where a design can have multiple granularities if it is described in a hierarchical fashion).
The structural gate level description is the prevalent starting point for many physical layout EDA (Electronic Design Automation) tools. The structural gate level description was the prevalent level of abstraction for digital design until the increases in complexity required a higher level of abstraction. A subset of the HDL behavioral description, commonly referred to as the RTL (Register Transfer Level) description, is now considered the starting point for Application Specific Integrated Circuit (ASIC) design.
The typical ASIC EDA methodology is to transform (with an aid of a synthesis tool) the HDL behavioral description of the design into a structural gate level description.
In order to perform effective partitioning and floorplanning of the design, the granularity of the design plays a critical role in achieving an optimum solution. Given the current ASIC EDA methodology, one has two choices for a starting point for the partitioning and floorplanning tasks: HDL behavioral description or structural gate level description. The HDL behavioral description is the preferred one, since it is the starting point of the ASIC EDA methodology and it is a familiar representation of the design to the designer. Both descriptions, the HDL behavioral description and the structural gate level description, can contain only two levels of object granularity: module/entity object granularity and gate object granularity. The module/entity granularity is rather “coarse”: a module typically has a large logic size. The gate granularity is rather “fine”: a gate typically has a very small logic size.
If module/entity granularity is used for the partitioning and floorplanning, the number of possible solutions is rather limited. This is a direct result of the “coarse” granularity of the module/entity objects. The large logic size of the module/entity objects provides for a small number of module/entity objects which results in a small number of possible solutions. Finding an optimum solution among limited number of possible solutions may not be achievable.
If gate granularity is used for the partitioning and floorplanning, the number of possible solutions is very large. This is a direct result of the “fine” granularity of the gate objects. The very small logic size of the gate objects provides for a very large number of gate objects which results in a very large number of possible solutions. Finding an optimum solution from a very large number of possible solutions can be very compute intensive.
In order to perform an effective and optimum partitioning and floorplanning of a design, an intermediate level of granularity, between the large module/entity granularity and the very small gate granularity, is required. This invention addresses the creation of this intermediate granularity in the HDL behavioral description of the design through the system and method of Process Encapsulation.
The lack of intermediate level of granularity also affects the synthesis of HDL behavioral descriptions with large logic sizes. The synthesis time of large logic size HDL behavioral description grows non-linearly with the logic size of the HDL behavioral description. Thus, for a very large logic size HDL behavioral description, the synthesis time can be prohibitive. In addition, the resulting synthesized structural gate level description of the HDL behavioral description does not retain all of the HDL signal and net names. The HDL signals are either eliminated (through optimization) or transformed in a non-deterministic fashion to a different name.
The prohibitive synthesis time for large logic size HDL behavioral descriptions and the elimination of most HDL signal names in the synthesized structural gate level description has a very negative impact on the EDA methodology of high-speed verification of ASICs using FPGAs. The prohibitive synthesis time increases the time to verification significantly. The transformation and/or elimination of HDL signal names in the synthesized structural gate level description renders the observability of HDL signal difficult or impossible. The present invention provides for a system and method of improving the synthesis time of large logic size HDL b
Kik Phallaka
Scheinberg Michael O.
Smith Matthew
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