Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-09
2002-04-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S626000, C438S627000, C438S629000, C438S675000, C438S672000, C438S687000, C438S688000
Reexamination Certificate
active
06368953
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor processing, and more particularly to a process for encapsulating an electroplated metal structure in a semiconductor device. This invention also relates to a metal-insulator-metal (MIM) capacitor in the device which incorporates such a metal structure.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor devices, metal lines are often embedded in dielectric layers in a multilevel structure, particularly in the latter stage (“back end of the line” or “BEOL”) of the fabrication process. In general, it is necessary to isolate the metal lines on one level from the other levels. This is typically done by providing a high-dielectric-constant barrier (for example, silicon nitride) between the levels.
A conventional BEOL process, providing an electroplated metal line in an interlevel dielectric and an interlevel barrier, is shown in
FIGS. 1A-1E
. An interlevel dielectric layer (such as SiO
2
)
10
has a feature
11
formed therein. A liner/adhesion promoter
12
for the plated line is deposited on the surface, including the sidewalls and bottom of feature
11
(FIG.
1
A). In the case of copper electroplating, layer
12
is typically a combination of tantalum nitride (in contact with the substrate
10
) and tantalum; layer
12
serves as a copper diffusion barrier while promoting adhesion to the substrate. As shown in
FIG. 1B
, a seed layer
13
for the metal to be plated is deposited over the entire surface. Plating is then performed on the entire surface, until feature
11
is filled in with plated metal
14
(see FIG.
1
C). To ensure that the entire feature is filled in, plating continues until an excess of plated metal appears in areas
15
outside feature
11
. This excess metal, along with the liner material in areas
15
, is then removed with a planarization process such as chemical-mechanical polishing (CMP), to yield a metal line as shown in FIG.
1
D. The plated metal
14
is surrounded by the liner
12
, except on the top surface
14
a.
In order to encapsulate the metal line (to prevent electrical shorts and degradation of the metal line due to electromigration and diffusion of the metal), the top surface of the interlayer dielectric
10
is blanketed with a dielectric layer
16
(see FIG.
1
E). This layer is typically silicon nitride. The high dielectric constant of layer
16
increases the overall dielectric constant of the level structure (which includes interlevel dielectric
10
, metal
14
and layer
16
). This has the effect of degrading the performance of the completed semiconductor device.
There is a need for an improved BEOL fabrication process in which the plated metal is encapsulated but the blanket dielectric layer is eliminated, so that the performance of the semiconductor device is enhanced.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a method of fabricating an encapsulated metal structure in a feature of a substrate, where the top surface of the substrate is exposed. This is done by covering the sidewalls and bottom of the feature with a first barrier layer; filling the feature with metal; forming a recess in the metal; and then depositing an additional barrier layer covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is then planarized, so that the top surface of the substrate is exposed. The planarization is preferably performed by CMP, and the feature is preferably filled by depositing a seed layer of metal in the feature and electroplating the metal.
According to one aspect of the invention, the recess in the metal is formed (preferably by CMP) so that a top surface of the metal is lower than the top surface of the substrate. A second barrier layer is then deposited on the top surface of the metal, and the first barrier layer and the second barrier layer are planarized. After planarization, the top surface of the substrate is exposed, the metal is encapsulated by the first barrier layer and the second barrier layer, and the second barrier layer is planar with the top surface of the substrate.
According to another aspect of the invention, planarizing the first barrier layer and the second barrier layer causes the top surface of the substrate to be exposed, and also causes a portion of the top surface of the metal to be exposed, with a remaining portion of the second barrier layer on the top surface of the metal. A second recess is then formed in the metal at the exposed portion thereof, and a third barrier layer is deposited on the top surface of the metal and on the remaining portion of the second barrier layer, thereby filling the second recess in the metal. The third barrier layer is then planarized so that the top surface of the substrate is exposed and the metal is encapsulated by the first barrier layer, the second barrier layer and the third barrier layer.
The present invention also provides a method of fabricating a metal-insulator-metal (MIM) capacitor which includes the above-described encapsulated metal structure. A first substrate layer has a feature formed therein, and an encapsulated metal structure is formed in the feature; the sidewalls and bottom of the feature are covered by a first barrier layer and the feature is filled with metal, covered by an additional barrier layer in contact with the first barrier layer. A second substrate layer is then deposited on the top surface of the first substrate layer and overlying the encapsulated metal structure; an opening is formed in the second substrate layer to expose the encapsulated metal structure. A dielectric layer is deposited on the second substrate layer, covering the sidewalls of the opening and the exposed encapsulated metal structure at the bottom of the opening. An additional layer is deposited, to cover the dielectric layer on the sidewalls and on the bottom of the opening and to fill the opening. The dielectric layer and the additional layer are then planarized.
According to an additional aspect of the invention, an encapsulated metal structure formed in a feature of a substrate is described. This structure includes a first barrier layer covering the sidewalls and bottom of the feature; metal filling the feature and having a recess formed therein, so that a top surface of the metal is lower than the top surface of the substrate; and an additional barrier layer covering the top surface of the metal and contacting the first barrier layer, so as to encapsulate the metal. The additional barrier layer is planarized so that the top surface of the substrate is exposed.
According to another aspect of the invention, a metal-insulator-metal (MIM) capacitor structure is described. This structure includes an encapsulated metal structure in a feature formed in a first substrate layer; the sidewalls and bottom of the feature are covered by a first barrier layer and the feature is filled with metal covered by an additional barrier layer in contact with the first barrier layer, to form a lower plate of the capacitor structure. The structure also includes a second substrate layer on the top surface of the first substrate layer; the second substrate layer has an opening formed therein overlying the encapsulated metal structure. A dielectric layer covers the sidewalls of the opening and a portion of the encapsulated metal structure at the bottom of the opening. An additional layer covers the dielectric layer on the sidewalls and bottom of the opening and fills the opening, to form an upper plate of the capacitor structure. The dielectric layer and the additional layer are planarized so that the top surface of the second substrate layer is exposed.
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patent: 3464855 (1969-09-01), Shaheen et al.
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patent: 5308796 (1994-05-01), Feldman et al.
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patent: 5821168 (1
Canaperi Donald
Krishnan Mahadevaiyer
Petrarca Kevin S.
Stein Kenneth Jay
Volant Richard P.
Anderdson Jay H.
Pham Thanhha
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