Encapsulated ferroelectric array

Details Encapsulated ferroelectric array Encapsulated ferroelectric array

2006-05-30

2006-05-30

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S297000

Reexamination Certificate

active

07053433

ABSTRACT:
A ferroelectric layer within an array of ferroelectric FETs is encapsulated between a bottom barrier dielectric layer and a top barrier dielectric layer extending beyond the ferroelectric layer. The ferroelectric FETs are formed on first conductivity type silicon, each having two second conductivity type silicon regions within the first conductivity type silicon separated by some distance. The two second conductivity type silicon regions forming a source and a drain with a channel region therebetween. A silicon dioxide layer is formed on the channel region, a bottom barrier dielectric layer is formed on the silicon dioxide layer, a ferroelectric layer is formed on the bottom barrier dielectric layer, a top barrier dielectric layer is formed on the ferroelectric layer, and an electrode layer is formed on the ferroelectric layer.

REFERENCES:
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patent: 6144060 (2000-11-01), Park et al.
patent: 6303456 (2001-10-01), Pricer et al.
patent: 6309956 (2001-10-01), Chiang et al.
patent: 6674110 (2004-01-01), Gnadinger
patent: 06169068 (1994-06-01), None

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