Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2005-08-18
2008-10-21
Clark, S. V (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S108000
Reexamination Certificate
active
07439100
ABSTRACT:
In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
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“Solderability”, efunda.com, engineering fundamentals, www.efunda.com/materials/solders/solderability.cfm, Copyright 2005 eFunda, 2 pages.
Fauty Joseph K.
Letterman, Jr. James P.
Thienpont Denise
Clark S. V
Jackson Kevin B.
Semiconductor Components Industries L.L.C.
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