Enabling resynchronization of a logic analyzer

Details Enabling resynchronization of a logic analyzer Enabling resynchronization of a logic analyzer

2011-06-07

2011-06-07

Maskulinski, Michael C (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07958404

ABSTRACT:
In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.

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patent: 2009/0323722 (2009-12-01), Sharma

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