Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-28
1999-10-26
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711119, 711129, 711161, 711162, 711170, 711173, G06F 1100
Patent
active
059745061
ABSTRACT:
A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.
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Elkington Susan G.
Fava Thomas F.
Lubbers Clark E.
Sicola Stephen J.
Umland Wayne H.
Digital Equipment Corporation
Hudgens Ronald C.
Swann Tod R.
Tzeng Fred F.
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