Enable signal generator counteracting delay variations for...

Details Enable signal generator counteracting delay variations for... Enable signal generator counteracting delay variations for...

2008-01-03

2009-08-11

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S233500, C365S208000, C365S194000, C365S196000, C365S195000, C365S190000, C327S288000, C327S285000, C327S281000, C327S278000

Reexamination Certificate

active

07573769

ABSTRACT:
A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

REFERENCES:
patent: 4692637 (1987-09-01), Shoji
patent: 6498512 (2002-12-01), Simon et al.
patent: 7084476 (2006-08-01), Gupta et al.
patent: 2002/0118036 (2002-08-01), Simon et al.

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