Emulation system having a scalable multi-level multi-stage progr

Details Emulation system having a scalable multi-level multi-stage progr Emulation system having a scalable multi-level multi-stage progr

1995-10-13

1996-11-12

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 44, 364488, 364578, H03K 19177

Patent

active

055743889

ABSTRACT:
A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the FPGA, inter-FPGA, interlogic boards, and inter-backplanes. More specifically, under the presently preferred embodiemnt, an on-chip 3-stage inter-logic element crossbar network is provided to each FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the FPGA. A two level two-stage inter-FPGA crossbard network is provided to interconnect the FPGAs and I/O pins of the logic board. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.

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patent: 5448496 (1995-09-01), Butts et al.
patent: 5452231 (1995-09-01), Butts et al.
Clos, "A Study of Non-Blocking Switching Networks," The Bell System Technical Journal, Mar. 1953, pp. 406-424.

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