Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-01-14
2003-05-20
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S059000
Reexamination Certificate
active
06567933
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital microprocessors, and more particularly to emulating and debugging digital microprocessors.
BACKGROUND OF THE INVENTION
As the technology for manufacturing integrated circuits advances, more and more logic functions may be included in a single integrated circuit device. Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions, such as, for example, those in a general-purpose microprocessor. The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the fabrication of the circuit be error free, as some manufacturing defects may prevent it from performing all of the functions that it is designed to perform. This requires verification of the design of the circuit and also various types of electrical testing after manufacture.
In conjunction with the stuck-fault modeling and associated test generation, other circuitry may be included in the VLSI circuit specifically designed to improving its testability. One type of test circuitry is a scan path in the logic circuit. A scan path consists of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. These latches can be loaded with a serial data stream (“scan in”) presetting the logic circuit nodes to a predetermined state. The logic circuit then can be exercised in normal fashion, with the result of the operation (at each of the nodes having a scan latch) stored in its respective latch. By serially unloading the contents of the latches (“scan out”), the result of the particular test operation at the associated nodes is read out and may be analyzed for improper node operation. Repetition of this operation with a number of different data patterns effectively tests all necessary combinations of the logic circuit, but with a reduced test time and cost compared to separately testing each active component or cell and all their possible interactions. Scan paths permit circuit initialization by directly writing to the latches (or registers) and directly observing the contents of the latches (or registers). Using scan paths helps to reduce the quantity of test vectors compared to traditional “functional mode” approaches. Techniques for scanning such data are discussed by E. J. McCluskey in
A Survey of Design for Testability Scan Techniques
, VLSI Design (Vol. 5, No. 12, pp. 38-61, December 1984).
Another solution is the test access port and boundary-scan architecture defined by the IEEE 1149.1 standard, a so-called JTAG test port. IEEE 1149.1 is primarily intended as a system test solution. The IEEE 1149.1 standard requires a minimum of four package pins to be dedicated to the test function. The IEEE 1149.1 standard requires boundary scan cells for each I/O buffer, which adds data delay to all normal operation function pins as well as silicon overhead. Although it has “hooks” for controlling some internal testability schemes, it is not optimized for chip-level testing. IEEE 1149.1 does not explicitly support testing of internal DC parametrics.
Software breakpoints (SWBP) provide another mechanism to allow the debug of microprocessor code and to evaluate performance. A SWBP is typically accomplished through opcode replacement, provided the program resides in a writable memory module which allows the opcode at the stop point to be replaced in memory with the software breakpoint opcode. In most machines, when a SWBP opcode reaches the first execute stage of an instruction execution pipeline, it causes the pipeline to stop advancing or trap to an interrupt service routine, and set a debug status bit indicating the pipeline has stopped or trapped. In processors classified as protected pipelines, instructions fetched into the pipeline after the SWBP are not executed. Instructions that are already in the pipeline are allowed to complete. To restart execution the pipeline can be cleared and then restarted by simply refetching the opcode at the SWBP memory address after the opcode is replaced in memory with the original opcode.
Testing and debugging such a complex pipeline is difficult, even when the techniques described in the preceding paragraphs are used. Aspects of the present invention provide improved methods and apparatus for chip-level testing, as well as system-level debugging.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with an aspect of the invention, a processor is provided with circuitry operable to execute code, with circuitry capable of processing debug events, such that processed debug events cause the normal execution of instructions to cease and further causes a debug event induced suspended state to be entered which supports interrupt processing.
The processor further has a debug event induced suspended state that can be selectively enabled to process combinations of maskable interrupts, non-maskable interrupts, and reset.
The processor further has a debug event induced suspended state that can be enabled to process combinations of maskable interrupts, non-maskable interrupts, and reset.
The processor further allows the next sequential instruction to be executed from the suspended state.
The processor has circuitry that allows a number of instructions to be grouped and be executed as if they are a single instruction
The processor has circuitry such that interrupts can be selectively serviced from the suspended state.
The processor also services interrupts from the suspended state independent of the state of any global interrupt enable mask.
The processor further processes a single instruction step commands in the suspend state such that it allows the service routine of any interrupts serviced from the suspended state to complete before processing the single instruction step command.
The processor further has circuitry that can prevent halt execution commands from being processed in the service routine of any interrupts defined as serviceable from the suspended state.
The processor has circuitry that allows the servicing of any interrupts defined as serviceable from the suspended state without regard to the state of a global interrupt enable signal.
REFERENCES:
patent: 5682310 (1997-10-01), Pedneau et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5828824 (1998-10-01), Swoboda
patent: 6003143 (1999-12-01), Kim et al.
patent: 6035422 (2000-03-01), Hohl et al.
patent: 6202174 (2001-03-01), Lee et al.
patent: 6230119 (2001-05-01), Mitchell
patent: 6289300 (2001-09-01), Brannick et al.
patent: 6324684 (2001-11-01), Matt et al.
Matt David R.
Swoboda Gary L.
Brady III W. James
Iqbal Nadeem
Laws Gerald E.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Emulation suspension mode with stop mode extension does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Emulation suspension mode with stop mode extension, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Emulation suspension mode with stop mode extension will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3084338