Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-01-14
2003-05-13
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S025000, C714S027000, C714S028000
Reexamination Certificate
active
06564339
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital microprocessors, and more particularly to emulating and debugging digital microprocessors.
BACKGROUND OF THE INVENTION
As the technology for manufacturing integrated circuits advances, more and more logic functions may be included in a single integrated circuit device. Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions, such as, for example, those in a general-purpose microprocessor. The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the fabrication of the circuit be error free, as some manufacturing defects may prevent it from performing all of the functions that it is designed to perform. This requires verification of the design of the circuit and also various types of electrical testing after manufacture.
In conjunction with the stuck-fault modeling and associated test generation, other circuitry may be included in the VLSI circuit specifically designed to improving its testability. One type of test circuitry is a scan path in the logic circuit. A scan path consists of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. These latches can be loaded with a serial data stream (“scan in”) presetting the logic circuit nodes to a predetermined state. The logic circuit then can be exercised in normal fashion, with the result of the operation (at each of the nodes having a scan latch) stored in its respective latch. By serially unloading the contents of the latches (“scan out”), the result of the particular test operation at the associated nodes is read out and may be analyzed for improper node operation. Repetition of this operation with a number of different data patterns effectively tests all necessary combinations of the logic circuit, but with a reduced test time and cost compared to separately testing each active component or cell and all their possible interactions. Scan paths permit circuit initialization by directly writing to the latches (or registers) and directly observing the contents of the latches (or registers). Using scan paths helps to reduce the quantity of test vectors compared to traditional “functional mode” approaches. Techniques for scanning such data are discussed by E. J. McCluskey in
A Survey of Design for Testability Scan Techniques,
VLSI Design (Vol. 5, No. 12, pp. 38-61, Dec. 1984).
Another solution is the test access port and boundary-scan architecture defined by the IEEE 1149.1 standard, a so-called JTAG test port. IEEE 1149.1 is primarily intended as a system test solution. The IEEE 1149.1 standard requires a minimum of four package pins to be dedicated to the test function. The IEEE 1149.1 standard requires boundary scan cells for each I/O buffer, which adds data delay to all normal operation function pins as well as silicon overhead. Although it has “hooks” for controlling some internal testability schemes, it is not optimized for chip-level testing. IEEE 1149.1 does not explicitly support testing of internal DC parametrics.
Software breakpoints (SWBP) provide another mechanism to allow the debug of microprocessor code and to evaluate performance. A SWBP is typically accomplished through opcode replacement, provided the program resides in a writable memory module which allows the opcode at the stop point to be replaced in memory with the software breakpoint opcode. In most machines, when a SWBP opcode reaches the first execute stage of an instruction execution pipeline, it causes the pipeline to stop advancing or trap to an interrupt service routine, and set a debug status bit indicating the pipeline has stopped or trapped. In processors classified as protected pipelines, instructions fetched into the pipeline after the SWBP are not executed. Instructions that are already in the pipeline are allowed to complete. To restart execution the pipeline can be cleared and then restarted by simply refetching the opcode at the SWBP memory address after the opcode is replaced in memory with the original opcode.
Testing and debugging such a complex pipeline is difficult, even when the techniques described in the preceding paragraphs are used. Aspects of the present invention provide improved methods and apparatus for chip-level testing, as well as system-level debugging.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
A digital system is provided with a processor, wherein the processor is operable to execute a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit. The processor has a test port circuitry for receiving test commands from a remote test host. There is interrupt circuitry for receiving a plurality of interrupt signals, operable to interrupt execution of the sequence of instructions. There is emulation circuitry for debug events connected to the test port circuitry, operable to cause the processor to enter a debug suspend state in response to a first debug event and to leave the debug suspend state to resume execution of the sequence of instructions in response to a command received by the test port circuitry, wherein execution of the sequence of instructions ceases while the processor is in the debug suspend state; wherein the processor is operable leave the debug suspend state in response to a first interrupt received by the interrupt circuitry to execute a corresponding first interrupt service routine (ISR). The emulation circuitry is further operable to cause the processor to enter a debug suspend state in response to a second debug event which occurs while the processor is executing the first ISR.
According to another aspect of the present invention, the emulation circuitry is further operable leave the debug suspend state in response to a second interrupt received by the interrupt circuitry to execute a corresponding second ISR to cause the processor to enter a debug suspend state in response to a third debug event which occurs while the processor is executing a second ISR.
According to another aspect of the present invention, there is debug frame counter (DFC) circuitry operable to store a debug frame number, such that the debug frame number distinguishes executing the first ISR from executing the second ISR. The processor is further operable to execute an instruction to initialize the DFC circuitry. The test port circuitry is operable to communicate the frame count number to the external test host.
According to another aspect of the present invention, there is debug frame register (DFR) circuitry, operable to store an expected frame count number in response to a command received by the test port circuitry. A first access command received by the test port circuitry is not performed if the frame count number is different from the expected frame count number.
According to another aspect of the present invention, a method is provided for operating a digital system comprising a microprocessor, wherein the microprocessor is operable to execute a sequence of instructions, comprising the steps of:
entering into a debug suspend state in response to a first debug event, such that execution of the sequence of instructions ceases while the processor is in the debug suspend state;
receiving an interrupt signal while in the debug suspend state;
processing the interrupt signal by executing a first interrupt service routine (ISR); and
entering into the debug suspend state in response to a second debug event during the step of processing the first ISR, such that execution of
Matt David R.
Swoboda Gary L.
Bonura Timothy M.
Brady III W. James
Iqbal Nadeem
Laws Gerald E.
Telecky , Jr. Frederick J.
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