Emulation of independent active DMA channels with a single...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing

Reexamination Certificate

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C710S029000, C710S038000

Reexamination Certificate

active

07660916

ABSTRACT:
The present invention utilizes a single DMA engine to process the requests of active DMA channels competing for transfer of data over a single bus. The invention employs two identical sets of DMA request registers which are connected to a processor. These register sets are connected through a switching means to the DMA engine. While a first DMA transfer represented by a first set of registers is active, the process enables preparation of the next request in a second set of registers. Upon completion of the first DMA transfer, the DMA engine is switched to commence processing of the DMA request represented by the second set of registers.

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patent: 7500028 (2009-03-01), Yamagishi

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