Emulating quasi-synchronous DRAM with asynchronous DRAM

Details Emulating quasi-synchronous DRAM with asynchronous DRAM Emulating quasi-synchronous DRAM with asynchronous DRAM

1997-03-13

1999-05-04

Robertson, David L.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365233, 711105, G06F 506

Patent

active

059013044

ABSTRACT:
A quasi-synchronous DRAM circuit uses a plurality of asynchronous DRAM macros organized in memory banks. An interface conversion circuit receives external synchronous control signals and generates internal control signals for each of the plurality of asynchronous DRAM macros. A data buffer circuit is connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus. The interface conversion circuit controls the data buffer to provide synchronous burst of data through frequency conversion.

REFERENCES:
patent: 4665495 (1987-05-01), Thaden
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 5033027 (1991-07-01), Amin
patent: 5148524 (1992-09-01), Harlin et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5276843 (1994-01-01), Tillinghast et al.
patent: 5291580 (1994-03-01), Bowden, III et al.
patent: 5404338 (1995-04-01), Murai et al.
patent: 5432707 (1995-07-01), Leung

Affiliated with

Also associated with

Rating

Emulating quasi-synchronous DRAM with asynchronous DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Emulating quasi-synchronous DRAM with asynchronous DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Emulating quasi-synchronous DRAM with asynchronous DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1876807