Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1997-03-04
2003-06-10
Le, Amanda T. (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C327S145000, C327S147000, C327S156000, C327S163000, C331S025000
Reexamination Certificate
active
06577695
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to phase-locked loop circuits, and more particularly to a phase-locked loop circuit which exhibits a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequency range.
2. Description of Related Art
Digital data transmission has become increasingly important in the modern communications era. The importance of modern digital data transmission drives the search for more efficient and effective phase-locked loops that are used in data communications systems.
FIG. 1
illustrates a prior art phase-locked loop (PLL)
10
feedback circuit. The PLL
10
is a feedback circuit that is often used to reduce an error term toward zero. In the case of the PLL, the error term is the phase difference between an input signal and a reference signal. The basic component building blocks of a PLL are a phase comparator
12
and an input-controlled oscillator (ICO)
14
. The PLL incorporates the ICO
14
in the feedback loop. An ICO is an oscillator whose output frequency is a function of its input. The phase comparator
12
compares the phase of the input signal on line
16
to the phase of the signal at the output of the ICO on line
18
. If the phase difference between these two signals is non-zero, the output frequency of the ICO
14
is adjusted in a manner which forces this difference towards zero. The output signal on line
20
is fed back to the ICO
14
to provide a signal that is related to the phase difference between the signals on lines
16
and
18
.
As is appreciated by those skilled in the art, such a PLL feedback system is often used to extract a baseband signal from a frequency modulated carrier in a communications system. Phase-locked loops are also widely used in communication systems for coherent carrier tracking, bit synchronization and symbol synchronization. The PLLs as used in the data communications system of the present invention are used to lock to a receive signal and to subsequently provide the receive clock for that signal. Typically, the PLL lock information generated from a data signal is poor, and is therefore not capable of pulling the PLL very far in frequency. Often the frequency range of the PLL is wider than this narrow “capture” range. Under these circumstances, the oscillation frequency of the PLL must somehow be brought close enough to the data signal frequency for the PLL to lock to the data signal. This can be done, as shown in
FIG. 1
, by first locking the PLL
10
to the frequency of a reference signal on line
22
, which is close in frequency to the data signal on line
24
. When the PLL
10
is locked to the reference signal on line
22
, the input of the PLL
10
is switched over to the data signal on line
24
. Although this procedure works, it requires control circuitry
26
to switch from the reference signal on line
22
to the data signal on line
24
, and then back again if phase lock is lost.
There is a need, therefore, for a phase-locked loop which has a wide frequency capture range for pulling the PLL within a predetermined frequency range, yet has a well-controlled and narrow frequency capture range for locking to the actual data signal, without the use of switching control circuitry such as control circuitry
26
.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a phase-locked loop that exhibits a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequency range.
The apparatus detects a frequency difference between at least one reference signal and a phase-locked loop (PLL) output signal, and generates a frequency error signal in response to the frequency difference. A phase difference is detected between a received input signal and the PLL output signal, and a phase error signal is generated in response to this phase difference. The frequency error signal and the phase error signal are combined, and this combined signal controls the frequency of the output signal.
One aspect of the invention is that the frequency error signal dominates the concurrently generated phase error signal when the frequency difference is outside of a predetermined frequency range. This dominating signal overdrives the phase error signal when the controlled oscillator frequency is outside of the predetermined frequency range.
In another embodiment of the present invention, a multiple-stage phase-locked loop (PLL) has an inherently wide actual frequency range and a narrow effective signal capture range. The PLL includes a first detection mechanism for detecting first phase differences between reference clocks and an output signal, and for generating a first phase error signal when the first phase differences fall outside of a predetermined frequency range. The PLL further includes a second detection mechanism for detecting second phase differences between a received input signal and the output signal, and for generating a second phase error signal in response thereto. A signal summing mechanism combines the first phase error signal and the second phase error signal, and allows the first phase error signal to overdrive the second phase error signal when both the first and second phase error signals are active. The PLL also includes an input-controlled oscillator to control the frequency of the output signal in response to the first and second phase error signals.
In yet another embodiment of the invention, a method is provided for phase-locking an output signal to a data signal. A frequency error signal is generated where a first frequency difference, measured by the frequency difference between a reference signal and the output signal, is outside of a predetermined frequency range. A phase error signal is generated for a second frequency difference measured by the frequency difference between the data signal and the output signal. Where the first frequency difference is outside of the predetermined frequency range, the frequency error signal overdrives the phase error signal. The frequency of the output signal is controlled with the phase error signal and the frequency error signal.
These and various other advantages and features of novelty which characterize the invention or point out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there is illustrated and described specific examples of an apparatus in accordance with the invention.
REFERENCES:
patent: 4787097 (1988-11-01), Rizzo
patent: 4942370 (1990-07-01), Shigemori
patent: 5446416 (1995-08-01), Lin et al.
patent: 5465277 (1995-11-01), Schreurs et al.
patent: 5525935 (1996-06-01), Joo et al.
patent: 6031428 (2000-02-01), Hill
Everitt James
Parker James
Le Amanda T.
Level One Communications
Merchant & Gould P.C.
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