Emptying packed data state during execution of packed data instr

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395563, 39580043, 395570, G06F 1200

Patent

active

059408596

ABSTRACT:
A method in a computer system which includes receiving a first instruction which indicates indicates termination of execution of instructions which operate upon packed data stored in a first storage area. The first storage area is used for modifying data responsive to execution of floating point instructions. A plurality of tags is associated with the first storage area indicating that locations in the first storage area are either empty or non-empty responsive to the execution of the floating point instructions which modify data contained in the first storage area. Responsive to the receiving of the first instruction which indicates termination of execution of instructions which operate upon the packed data stored in the first storage area, the method sets only the plurality of tags to an empty state. In different embodiments, setting of the plurality of tags to a non-empty state occurs responsive to receiving a second instruction. The second instruction (or instructions) specifies an operation upon packed data stored in the first storage area. The setting of the plurality of tags indicates execution of instructions which operate upon the packed data. This method advantageously provides a means for clearing the packed data state at the end of blocks of packed data instructions to leave the floating point state in a clear condition for subsequent operations (e.g. floating point calculations).

REFERENCES:
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4229801 (1980-10-01), Whipple
patent: 4393468 (1983-07-01), New
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4498177 (1985-02-01), Larson
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4771379 (1988-09-01), Ando et al.
patent: 4989168 (1991-01-01), Kuroda et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5008812 (1991-04-01), Bhandarkar et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5187679 (1993-02-01), Vassiliadis
patent: 5241635 (1993-08-01), Papadopoulos et al.
patent: 5267350 (1993-11-01), Matsubara et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5481719 (1996-01-01), Ackerman et al.
patent: 5499352 (1996-03-01), Clift et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5522051 (1996-05-01), Sharangpani et al.
patent: 5535397 (1996-07-01), Durante et al.
patent: 5537606 (1996-07-01), Byrne et al.
patent: 5546554 (1996-08-01), Yung et al.
patent: 5560035 (1996-09-01), Garg et al.
patent: 5634118 (1997-05-01), Blomgren
patent: 5651125 (1997-07-01), Witt et al.
patent: 5677862 (1997-10-01), Peleg et al.
patent: 5687336 (1997-11-01), Shen et al.
patent: 5701508 (1997-12-01), Glew et al.
patent: 5721892 (1998-02-01), Peleg et al.
patent: 5760792 (1998-06-01), Holt et al.
i860.sup.TM Microprocessor Family Programmer's Reference Manual, Intel Corporation (1992) Ch. 2, 9, 10, 11.
J. Shipnes, Graphics Processing with the 88110 RISC Microprocessor, IEEE (1992), pp. 169-174.
MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1991).
Errata to MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1992), pp. 1-11.
MC88110 Programmer's Reference Guide, Motorola Inc. (1992), pp. 1-4.
i860 .sup.TM Microprocessor Family Programmer's Reference Manual, Intel Corporation (1992), Ch. 1, 3, 8, 12.
R. B. Lee, Accelerating Multimedia With Enhanced Microprocessors, IEEE Micro (Apr. 1995), pp. 22-32.
TMS320C2x User's Guide, Texas Instruments (1993) pp 3-2 through 3-11; 3-28 through 3-34; 4-1 through 4-22; 4-41; 4-103; 4-119 through 4-120; 4-122; 4-150 through 4-151.
L. Gwennap, New PA-RISC Processor Decodes MPEG Video, Microprocessor Report (Jan. 1994), pp. 16, 17.
SPARC Technology Business, UltraSPARC Multimedia Capabilities On-Chip Support for Real-Time Video and Advanced Graphics, Sun Microsystems (Sep. 1994).
Y. Kawakami et al., LSI Applications: A Single-Chip Digital Signal Processor for Voiceband Applications, Solid State Circuits Conference, Digest of Technical Papers; IEEE International (1980).
B. Case, Philips Hopes to Displace DSPs with VLIW, Microprocessor Report (Dec. 94), pp. 12-18.
N. Margulis, i860 Microprocessor Architecture, McGraw-Hill, Inc. (1990) Ch. 6, 7, 8, 10, 11.
Pentium Processor User's Manual, vol. 3: Architecture and Programming Manual, Intel Corporation (1993), Ch. 1, 3, 4, 6, 8, and 18.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Emptying packed data state during execution of packed data instr does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Emptying packed data state during execution of packed data instr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Emptying packed data state during execution of packed data instr will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-326064

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.