Emitter coupled logic (ECL) gate which generates intermediate si

Details Emitter coupled logic (ECL) gate which generates intermediate si Emitter coupled logic (ECL) gate which generates intermediate si

1996-05-02

1998-05-12

Westin, Edward

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

326 80, H03K 19086

Patent

active

057511691

ABSTRACT:
A fully differential, low voltage ECL gate (300) receives differential input signals (A, Ax, B, Bx) and provides them to first and second differential amplifiers (306, 328). The first differential amplifier (306) amplifies and level shifts the differential input (A, Ax) to provide a differential output (OUTx). The second differential amplifier amplifies the second differential input (B, Bx) to provide an amplified output, OUT. The amplified output signal, OUT, provides a different voltage level than that provided by amplified level shifted output signal, OUTx. The amplified level shifted output (OUTx) of the first differential amplifier (306) is then compared to the amplified output (OUT) of the second differential amplifier (328) to provide either an AND gate or an OR gate function.

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Razavi, B., Ota, Y., Shwartz, R.G., "Design Techniques for Low-Voltage High-Speed Digital Bipolar Circuits," IEEE, Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994; pp. 332-339.

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