Emitter coupled logic (ECL) gate

Details Emitter coupled logic (ECL) gate Emitter coupled logic (ECL) gate

1996-07-01

1998-11-03

Yoo, Do Hyun

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

326 52, 326 54, 326127, H03K 19086

Patent

active

058314547

ABSTRACT:
An emitter coupled logic gate (300) avoids the use of stacked transistors by utilizing a single-ended bias input and positive feedback (320) between first and second transistors (304, 306) to achieve an inverter function. The inverter (300) can also be configured as an OR gate (500) by adding a third transistor biased by second single-ended logic input. The OR gate (500) can be configured into an exclusive OR gate (901) by converting another set of single-ended bias inputs into what can be either differential or non-differential outputs (921, 923) to be used as inputs to OR gate (919).

REFERENCES:
patent: 4516039 (1985-05-01), Matsuzaki et al.
patent: 5079452 (1992-01-01), Lain et al.
patent: 5148059 (1992-09-01), Chen et al.
patent: 5220212 (1993-06-01), Sinh
patent: 5250860 (1993-10-01), Chu et al.
patent: 5289055 (1994-02-01), Razavi
Razavi, B., Ota, Y., Swartz, R. G., "Design Techniques for Low-Voltage High-Speed Digital Bipolar Circuits," IEEE, Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994.

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