Emitter coupled logic circuit

Details Emitter coupled logic circuit Emitter coupled logic circuit

1993-10-07

1995-07-04

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

377 70, 377 73, H03K 1920

Patent

active

054303362

ABSTRACT:
A emitter coupled logic circuit is reduced in circuit scale, while maintaining the speed of shift registers and compatibility with analog circuits. When data held in the first self-holding circuit section 41 or the second self-holding section 42 is deleted, the threshold voltage VTH applied to the base electrodes of the first and third transistors Q41 and Q43 is set outside the logical amplitude. When data is transferred, also, the threshold voltage VTH is set at a value intermediate to the logical amplitude. Because of this the data held in the first and second self-holding circuit sections can be reliably deleted without an increase in the number of elements. Further, it enables a shift register to be composed of at least 50% fewer elements than before, and can bring about a marked improvement in integration and a marked reduction in power consumption, by arranging a first self-holding circuit section consisting of first and second transistors, a second self-holding circuit section consisting of third and fourth transistors, and a switching circuit alternately switching the operational states of the first and second self-holding circuit sections, and transferring data retained in the first self-holding circuit section to the second self-holding circuit section on a collector current led from the collector electrode of the third transistor to the collector electrode of the second transistor.

REFERENCES:
patent: 4692641 (1987-09-01), Highton
patent: 4733218 (1988-03-01), Traa
patent: 5103117 (1992-08-01), Voorman
patent: 5134312 (1992-07-01), Jones

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